Abstract: A first system and method relates to an analog current-mode method using branch systems. In the analog current-mode implementation, multiple branches systems can be scaled according to filter coefficients and switched using known data points. Positive coefficients can add current to the summing node, while negative coefficients can remove current from the summing node. Switches can be implemented with quick charge/discharge paths in order to operate at very high data rates. A second system and method relates to a digital look-up table based high-speed implementation. In the digital implementation, outputs can be pre-calculated as an n-bit output word that drives an n-bit DAC. Each bit of the n-bit word can then described as an independent function of the known data points. Each such function can be implemented as a high-speed combinational logic block. Both systems and methods enable the implementation of pulse shaping filters for multi-gigabit per second data transmission.

Abstract: A method and process for establishing a mapped network of access points for a user of a wireless device is provided. A unique and customized network is selected from cellular connections, private wireless connections, public wireless connections, and wireless card connections such that a unique and personalized control of wireless connectivity may be established. Greater wireless resources are thus made available and provide for greater connectivity and improved battery life for a user's device.

Abstract: An analog to digital converter for operating at high speeds can be implemented with a micro-comparator/sampler, an encoder, and a selector. The micro-comparator includes an input from an antenna of a receiver/transceiver system; a transistor pair; reset transistor; cascaded inverters; an inverter circuit; a buffer; and a D flip flop circuit. Depending on the number of micro-comparator/samplers placed in parallel, a number of bits can be generated. For example, 15 bits from 15 different micro-comparator/samplers can be inserted into a 15 to 4 bit encoder to generate 4 bits.

Abstract: A flange extender for use with an injection device is described. The flange extender includes first and second flange extender pieces and a locking mechanism to lock the first and second flange extender pieces to one another. In one embodiment, the locking mechanism includes each piece having a locking finger extending from the piece and an aperture adapted to receive the locking finger. The first and second flange extender pieces extend in a direction transverse to a main axis of the injection device to thereby provide a surface area for manual manipulation of the injection device during an injection. The first and second flange extender pieces also attach to each other on opposite sides of the injection device.

Abstract: A method of fabricating an ultra-high frequency module is disclosed. The method includes providing a top layer; drilling the top layer; milling the top layer; providing a bottom; milling the bottom layer to define a bottom layer cavity; aligning the top layer and the bottom layer; and adhering the top layer to the bottom layer. The present invention also includes an ultra-high frequency module operating at ultra-high speeds having a top layer, the top layer defining a top layer cavity; a bottom layer, the bottom layer defining a bottom layer cavity; and an adhesive adhering both the top layer to the bottom layer, wherein the top layer and the bottom layer are formed from a large area panel of a printed circuit board.

Abstract: A tunable capacitor device may be provided in accordance with example embodiments of the invention. The tunable capacitor device may include a first capacitor; a second capacitor; a third capacitor, where the first, second, and third capacitors are connected in series, wherein the second capacitor is positioned between the first capacitor and the second capacitor; and at least one switch transistor, where the at least one switch transistor is connected in parallel with the second capacitor.

Abstract: A method for interference suppression, including receiving a sample of an aggressor communication signal from a sensor embedded in a flex circuit, emulating interference that the aggressor communication signal imposes on a victim communication signal, and suppressing the imposed interference in response to applying the emulated interference to the victim communication signal. In other aspects, the flex circuit comprises a plurality of traces running substantially parallel to one another along a surface of the flex circuit, and the sensor comprises one of the plurality of traces and one of a plurality of traces of another flex circuit. In still other aspects, the flex circuit comprises a plurality of traces running substantially parallel to one another and the sensor comprises a trace of the flex circuit running perpendicular to the plurality of traces running substantially parallel to one another.

Abstract: Systems and methods for provided for linearization systems and methods for variable attenuators. The variable attenuators can include series transistors along a main signal path from the input to output, as well as shunt transistors. A bootstrapping body bias circuit can be used with one or of the series transistors to allow the body of a connected transistor to swing responsive to a received RF input signal. As the RF signal increases and affects the gate-to-source voltage difference of a transistor, a bootstrapping body bias circuit can adaptively adjust the threshold voltage of the connected transistor and compensate the channel resistance variation resulting from gate-to-source voltage swing. The bootstrapping body bias circuit can be implemented using passive elements, active elements, or a combination thereof.

Abstract: Systems and methods may be provided for a CMOS RF antenna switch. The systems and methods for the CMOS RF antenna switch may include an antenna that is operative to transmit and receive signals over at least one radio frequency (RF) band, and a transmit switch coupled to the antenna, where the transmit switch is enabled to transmit a respective first signal to the antenna and disabled to prevent transmission of the first signal to the antenna. the systems and methods for the CMOS RF antenna switch may further include a receiver switch coupled to the antenna, where the receiver switch forms a filter when enabled and a resonant circuit when disabled, where the filter provides for reception of a second signal received by the antenna, and where the resonant circuit blocks reception of at least the first signal.

Abstract: A system for suppressing interference imposed on a victim communication signal by an aggressor communication signal including a circuit that comprises an input port, an output port, and a signal processing circuit connected between the input port and the output port, the signal processing circuit being operative to produce an interference compensation signal at the output port, for application to the victim communication signal, via processing a sample of the aggressor communication signal transmitted through the input port, and the input port being configured to connect to a sampling system that includes a first circuit trace running along a surface of a flex circuit of a portable wireless device that is dedicated to sensing the aggressor communication signal flowing on a second circuit trace running along the surface of the flex circuit.

Abstract: Systems and methods for providing a self-mixing adaptive bias circuit that may include a mixer, low-pass filter or a phase shifter, and a bias feeding block. The self-mixing adaptive bias circuit may generate an adaptive bias signal depending on input signal power level. As the input power level goes up, the adaptive bias circuit increases the bias voltage or bias current such that the amplifier will save current consumption at low power operation levels and obtain better linearity at high power operation levels compared to conventional biasing techniques. Moreover, the adaptive bias output signal can be used to cancel the third-order intermodulation terms (IM3) to further enhance the linearity as a secondary effect.

Abstract: An analog multi-gigabit receiver and/or transceiver can be implemented for the reception and demodulation of multi-gigabits quadrature phase shift keying (QPSK) modulated using a CMOS (complementary metal-oxide semiconductor) process. Further, an analog multi-gigabit receiver and/or transceiver can be implemented for the reception and demodulation of multi-gigabits binary phase shift keying (BPSK), minimum shift keying (MSK), and/or amplitude shift keying (ASK) signal modulated in CMOS processes.

Abstract: An analog to digital converter for operating at high speeds can be implemented with a micro-comparator/sampler, an encoder, and a selector. The micro-comparator includes an input from an antenna of a receiver/transceiver system; a transistor pair; reset transistor; cascaded inverters; an inverter circuit; a buffer; and a D flip flop circuit. Depending on the number of micro-comparator/samplers placed in parallel, a number of bits can be generated. For example, 15 bits from 15 different micro-comparator/samplers can be inserted into a 15 to 4 bit encoder to generate 4 bits.

Abstract: A voltage controlled oscillator-phase lock loop (VCO-PLL) system includes a voltage controlled oscillator (VCO) system implementing four-channel architecture, such that two bands support two channels; a phase-locked-loop (PLL) system; and a mixer system. The VCO system further includes a control circuit; a first cross-coupled oscillator system adapted to receive a source voltage; a second cross-coupled oscillator system adapted to receive the source voltage; and a plurality of isolation buffer systems adapted to protect the first and second cross-coupled oscillator systems.

Abstract: Systems and methods for provided for linearization systems and methods for variable attenuators. The variable attenuators can include series transistors along a main signal path from the input to output, as well as shunt transistors. A bootstrapping body bias circuit can be used with one or of the series transistors to allow the body of a connected transistor to swing responsive to a received RF input signal. As the RF signal increases and affects the gate-to-source voltage difference of a transistor, a bootstrapping body bias circuit can adaptively adjust the threshold voltage of the connected transistor and compensate the channel resistance variation resulting from gate-to-source voltage swing. The bootstrapping body bias circuit can be implemented using passive elements, active elements, or a combination thereof.

Abstract: A system for suppressing interference imposed on a victim communication signal by an aggressor communication signal including a circuit that comprises an input port, an output port, and a signal processing circuit connected between the input port and the output port, the signal processing circuit being operative to produce an interference compensation signal at the output port, for application to the victim communication signal, via processing a sample of the aggressor communication signal transmitted through the input port, and the input port being configured to connect to a sampling system that includes a first circuit trace running along a surface of a flex circuit of a portable wireless device that is dedicated to sensing the aggressor communication signal flowing on a second circuit trace running along the surface of the flex circuit.

Abstract: A SPDT or SPMT switch may include a transformer having a primary winding and a secondary winding, where a first end of the secondary winding is connected to a single pole port, where a first end of the primary winding is connected to a first throw port; a first switch having a first end and a second end, where the first end is connected to ground; and a second switch, where a second end of the secondary winding is connected to both a second end of the first switch and a first end of the second switch, where a second end of the second switch is connected to a second throw port, where the first switch controls a first communication path between the single pole port and the first throw port, and where the second switch controls a second communication path between the second throw port and the single pole port.

Abstract: A receiver system and a demodulator system are configured to receive and demodulate, respectively, multi-gigabit millimeter wave signals being wirelessly transmitted in the unlicensed wireless band near 60 GHz.

Abstract: Signals propagating on an aggressor communication channel can cause interference in a victim communication channel. A sensor coupled to the aggressor channel can obtain a sample of the aggressor signal. The sensor can be integrated with or embedded in a system, such as a flex circuit or a circuit board, that comprises the aggressor channel. The sensor can comprise a dedicated conductor or circuit trace that is near an aggressor conductor, a victim conductor, or an EM field associated with the interference. An interference compensation circuit can receive the sample from the sensor. The interference compensation circuit can have at least two operational modes of operation. In the first mode, the circuit can actively generate or output a compensation signal that cancels, corrects, or suppresses the interference. The second mode can be a standby, idle, power-saving, passive, or sleep mode.

Abstract: An integrated power amplifier can include a carrier amplifier, where the carrier amplifier is connected to a first quarter wave transformer at the input of the carrier amplifier.