Abstract: An integrated power amplifier can include a carrier amplifier, where the carrier amplifier is connected to a first quarter wave transformer at the input of the carrier amplifier.

Abstract: Systems and methods for providing an adaptive bias circuit that may include a differential amplifier, low-pass filter, and common source amplifier or common emitter amplifier. The adaptive bias circuit may generate an adaptive bias output signal depending on input signal power level. As the input power level goes up, the adaptive bias circuit may increase the bias voltage or bias current of the adaptive bias output signal. A power amplifier (e.g., a differential amplifier) may be biased according to the adaptive bias output signal in order to reduce current consumption at low power operation levels.

Abstract: Embodiments of the invention may provide for a CMOS antenna switch, which may be referred to as a CMOS SPDT switch. The CMOS antenna switch may operate at a plurality of frequencies, perhaps around 900 MHz, 1.9 GHz and 2.1 GHz according to an embodiment of the invention. The CMOS antenna switch may include both a receiver switch and a transmit switch. The receiver switch may utilize a multi-stack transistor with body substrate switching and attachment of external capacitor between drain and gate to block high power signals from the transmit path as well as to maintain low insertion loss at the receiver path. Exemplary embodiments of the CMOS antenna switch may provide for 38 dBm P 0.1 dB at multi bands (e.g., 900 MHz, 1.8 GHz, and 2.1 GHz). In addition, ?60 dBc second and third harmonic performance up to 30 dBm input, may be obtained according to example embodiments of the invention.

Abstract: A wireless communication system can comprise two or more antennas that interfere with one another via free space coupling, surface wave crosstalk, dielectric leakage, or other interference effect. The interference effect can produce an interference signal on one of the antennas. A cancellation device can suppress antenna interference by generating an estimate of the interference signal and subtracting the estimate from the interference signal. The cancellation device can generate the estimate based on sampling signals on an antenna that generates the interference or on an antenna that receives the interference. The cancellation device can comprise a model of the crosstalk effect. Transmitting test signals on the communication system can define or refine the model.

Abstract: Systems and methods are provided for power amplifiers with discrete power control. The systems and methods may include a plurality of unit power amplifiers; a plurality of primary windings, wherein each primary winding is connected to at least one respective output port of a respective one the plurality of unit power amplifiers; a secondary winding inductively coupled to the plurality of primary windings, where the secondary winding provides an overall output; a bias controller, where the bias controller provides a respective bias voltage based at least in part on a level of output power to one or more of the plurality of unit power amplifiers; and a switch controller, where the switch controller operates to activate or deactivate at least one of the plurality of unit power amplifiers via a respective control signal.

Abstract: Signals propagating on an aggressor communication channel can cause detrimental interference in a victim communication channel. A signal processing circuit can generate an interference cancellation signal that, when applied to the victim communication channel, cancels the detrimental interference. The signal processing circuit can dynamically adjust or update two or more aspects of the interference cancellation signal, such as an amplitude or gain parameter and a phase or delay parameter. Via the dynamic adjustments, the signal processing circuit can adapt to changing conditions, thereby maintaining an acceptable level of interference cancellation in a fluctuating operating environment. A control circuit that implements the parametric adjustments can have at least two modes of operation, one for adjusting the amplitude parameter and one for adjusting the phase parameter. The modes can be selectable or can be intermittently available, for example.

Abstract: An analog multi-gigabit receiver and/or transceiver can be implemented for the reception and demodulation of multi-gigabits quadrature phase shift keying (QPSK) modulated using a CMOS (complementary metal-oxide semiconductor) process. Further, an analog multi-gigabit receiver and/or transceiver can be implemented for the reception and demodulation of multi-gigabits binary phase shift keying (BPSK), minimum shift keying (MSK), and/or amplitude shift keying (ASK) signal modulated in CMOS processes.

Abstract: Systems and methods may include a signal component separator that receives a non-constant envelope input signal and at least one phase offset value, and generates first digital phase data and second digital phase data; at least one digital phase modulator that receives the first phase data and the second phase data and operates with a frequency synthesizer to generate a first component signal having a first constant envelope and a second component signal having a second constant envelope; at least one power amplifier that amplifies the first component signal and the second component signal; a non-isolated power combiner that combines the first amplified component signal and the second amplified component signal to generate an output signal having a non-constant envelope; and a mismatch compensator that monitors the output signal to determine the at least one phase offset value, where the at least one phase offset value is utilized by the signal component separator for phase adjustment.

Abstract: Systems and methods may be provided for a LINC system having a level-shifting LINC amplifier. The systems and methods may include a dynamic power supply that is adjustable to provide at least a first voltage supply level and a second voltage supply level higher than the first voltage supply level; a first power amplifier that amplifies a first component signal to generate a first amplified signal; a second power amplifier that amplifiers a second component signal to generate a second amplified signal, where the first component signal and the second component signal are components of an original signal, where the first component signal and the second component signal each have a constant envelope, and where the original signal has a non-constant envelope, and where the first and second power amplifiers are biased at the first voltage supply level or the second voltage supply level based upon an analysis of an amplitude of the original signal.

Abstract: Embodiments of the invention may provide for a frequency synthesizer capable to generate an output signal in which the frequency is a fractional portion of the reference frequency without a fractional divider. Based on mathematical relationship (“relatively prime”) between the reference frequency and other injection frequencies mixed with the output signal of a voltage controlled oscillator, the synthesizer is able to generate signals evenly spaced in the frequency domain like Fractional-N PLLs. The synthesizer may include an Integer-N PLL, a SSB mixer, frequency dividers, and frequency multipliers. A Integer-N PLL may include a Phase and Frequency Detector, a Charge Pump, a Loop Filter and a Dual Modulus Divider. By not requiring a fractional divider, the frequency synthesizer is able to avoid adopting any compensation circuits such as Sigma-Delta modulator to suppress fractional spurs. Therefore, the chip area, power consumption and complexity will be reduced considerably.

Abstract: Systems and methods may be provided for a power amplifier system. The systems and methods may include a plurality of power amplifiers, where each power amplifier includes at least one output port. The systems and methods may also include a plurality of primary windings each having a first number of turns, where each primary winding is connected to at least one output port of the plurality of power amplifiers, and a single secondary winding inductively coupled to the plurality of primary windings, where the secondary winding includes a second number of turns greater than the first number of turns.

Abstract: Example embodiments of the invention may provide for active baluns. An example active balun may include a resonator that may convert a single-ended input signal to at least two differential input signals, and a differential switching block that includes first and second transistors that each receive a respective one of the at least two differential input signals from the resonator, where the first and second transistors may be cross-coupled to each other to provide a first differential output signal and a second differential output signal. An example active balun may further include one or more loads connected to the first and second differential output signals, and one or more stacked inverters that may provide a first output port and a second output port, where the first output port may be responsive to the first differential output signal and the second output port may be responsive to the second differential output signal.

Abstract: Embodiments of the invention may provide for an LC quadrature oscillator that includes two LC oscillators that are cross-coupled with each other to generate I/Q clock signals and a phase and amplitude mismatch compensator. The phase and amplitude mismatch detector may include an amplitude mismatch detector, a transconductor, and a capacitor for compensating for both phase and amplitude mismatches between I/Q clock signals generated in the LC quadrature oscillator.

Abstract: The present invention describes a receiver assembly for receiving an analog signal and converting the analog signal to a digital signal. The receiver assembly is, preferably, capable of receiving a signal operating at approximately 60 GHz. The receiver assembly includes a filter, a down converter, a demodulator, a latch, a FIFO, and a logic circuit. A method of converting the 60 GHz analog signal to a digital signal is also described.

Abstract: Embodiments of the invention may provide for power amplifier systems and methods. The systems and methods may include a power amplifier that generates a first differential output signal and a second differential output signal, a primary winding comprised of a plurality of primary segments, where a first end of each primary segment is connected to a first common input port and a second end of each primary segment is connected to a second common input port, where the first common input port is operative to receive the first differential output signal, and where the second common input port is operative to receive the second differential output signal, and a single secondary winding inductively coupled to the plurality of primary segments.

Abstract: Embodiments of the invention may provide for power amplifier systems and methods. The systems and methods may include a power amplifier that generates a first differential output signal and a second differential output signal, a primary winding comprised of a plurality of primary segments, where a first end of each primary segment is connected to a first common input port and a second end of each primary segment is connected to a second common input port, where the first common input port is operative to receive the first differential output signal, and where the second common input port is operative to receive the second differential output signal, and a single secondary winding inductively coupled to the plurality of primary segments.

Abstract: Example embodiments of the invention may provide systems and methods for a power amplifier. The systems and methods may include a first common-source device having a first source, a first gate, a first drain, and a first body, where the first source is connected to the first body, and wherein the first gate is connected to an input port. The systems and methods may further include a second common-gate device having a second source, a second gate, a second drain, and a second body, where the second source is connected to the first drain, where the second source is further connected to the second body, and where the second drain is connected to an output port.

Abstract: Example embodiments of the invention may provide systems and methods for multiple transformers. The systems and methods may include a first transformer that may include a first primary winding and a first secondary winding, where the first primary winding may be inductively coupled to the first secondary winding, where the first transformer may be associated with a first rotational current flow direction in the first primary winding.

Abstract: Example embodiments of the invention may provide systems and methods for a power amplifier. The systems and methods may include a first common-source device having a first source, a first gate, a first drain, and a first body, where the first source is connected to the first body, and wherein the first gate is connected to an input port. The systems and methods may further include a second common-gate device having a second source, a second gate, a second drain, and a second body, where the second source is connected to the first drain, where the second source is further connected to the second body, and where the second drain is connected to an output port.

Abstract: Embodiments of the invention may provide for power amplifier systems and methods. The systems and methods may include a power amplifier that generates a first differential output signal and a second differential output signal, a primary winding comprised of a plurality of primary segments, where a first end of each primary segment is connected to a first common input port and a second end of each primary segment is connected to a second common input port, where the first common input port is operative to receive the first differential output signal, and where the second common input port is operative to receive the second differential output signal, and a single secondary winding inductively coupled to the plurality of primary segments.