Patents by Inventor Joy Laskar

Joy Laskar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100127780
    Abstract: Systems and methods are provided for power amplifiers with discrete power control. The systems and methods may include a plurality of unit power amplifiers; a plurality of primary windings, wherein each primary winding is connected to at least one respective output port of a respective one the plurality of unit power amplifiers; a secondary winding inductively coupled to the plurality of primary windings, where the secondary winding provides an overall output; a bias controller, where the bias controller provides a respective bias voltage based at least in part on a level of output power to one or more of the plurality of unit power amplifiers; and a switch controller, where the switch controller operates to activate or deactivate at least one of the plurality of unit power amplifiers via a respective control signal.
    Type: Application
    Filed: November 17, 2009
    Publication date: May 27, 2010
    Applicant: SAMSUNG ELECTRO-MECHANICS COMPANY
    Inventors: Kyu Hwan An, Dong Ho Lee, Chang-Ho Lee, Joy Laskar
  • Patent number: 7725079
    Abstract: Signals propagating on an aggressor communication channel can cause detrimental interference in a victim communication channel. A signal processing circuit can generate an interference cancellation signal that, when applied to the victim communication channel, cancels the detrimental interference. The signal processing circuit can dynamically adjust or update two or more aspects of the interference cancellation signal, such as an amplitude or gain parameter and a phase or delay parameter. Via the dynamic adjustments, the signal processing circuit can adapt to changing conditions, thereby maintaining an acceptable level of interference cancellation in a fluctuating operating environment. A control circuit that implements the parametric adjustments can have at least two modes of operation, one for adjusting the amplitude parameter and one for adjusting the phase parameter. The modes can be selectable or can be intermittently available, for example.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: May 25, 2010
    Assignee: Quellan, Inc.
    Inventors: Andrew Joo Kim, Edward Gebara, Bruce C. Schmukler, Mark W. Dickmann, Michael F. Farrell, Michael G. Vrazel, David Anthony Stelliga, Joy Laskar, Charles E. Summers
  • Publication number: 20100093299
    Abstract: An analog multi-gigabit receiver and/or transceiver can be implemented for the reception and demodulation of multi-gigabits quadrature phase shift keying (QPSK) modulated using a CMOS (complementary metal-oxide semiconductor) process. Further, an analog multi-gigabit receiver and/or transceiver can be implemented for the reception and demodulation of multi-gigabits binary phase shift keying (BPSK), minimum shift keying (MSK), and/or amplitude shift keying (ASK) signal modulated in CMOS processes.
    Type: Application
    Filed: October 25, 2007
    Publication date: April 15, 2010
    Applicant: Georgia Tech Research Corporation
    Inventors: Stephane Pinel, Joy Laskar, David Yeh, Bevin George Perumana, Saikat Sarkar
  • Publication number: 20100073052
    Abstract: Embodiments of the invention may provide for a frequency synthesizer capable to generate an output signal in which the frequency is a fractional portion of the reference frequency without a fractional divider. Based on mathematical relationship (“relatively prime”) between the reference frequency and other injection frequencies mixed with the output signal of a voltage controlled oscillator, the synthesizer is able to generate signals evenly spaced in the frequency domain like Fractional-N PLLs. The synthesizer may include an Integer-N PLL, a SSB mixer, frequency dividers, and frequency multipliers. A Integer-N PLL may include a Phase and Frequency Detector, a Charge Pump, a Loop Filter and a Dual Modulus Divider. By not requiring a fractional divider, the frequency synthesizer is able to avoid adopting any compensation circuits such as Sigma-Delta modulator to suppress fractional spurs. Therefore, the chip area, power consumption and complexity will be reduced considerably.
    Type: Application
    Filed: September 21, 2009
    Publication date: March 25, 2010
    Applicant: Samsung Electro-Mechanics Company, Ltd
    Inventors: Jaehyouk Choi, Jongmin Park, Kyutae Lim, Chang-Ho Lee, Haksun Kim, Joy Laskar
  • Publication number: 20100074367
    Abstract: Systems and methods may include a signal component separator that receives a non-constant envelope input signal and at least one phase offset value, and generates first digital phase data and second digital phase data; at least one digital phase modulator that receives the first phase data and the second phase data and operates with a frequency synthesizer to generate a first component signal having a first constant envelope and a second component signal having a second constant envelope; at least one power amplifier that amplifies the first component signal and the second component signal; a non-isolated power combiner that combines the first amplified component signal and the second amplified component signal to generate an output signal having a non-constant envelope; and a mismatch compensator that monitors the output signal to determine the at least one phase offset value, where the at least one phase offset value is utilized by the signal component separator for phase adjustment.
    Type: Application
    Filed: September 17, 2009
    Publication date: March 25, 2010
    Applicant: SAMSUNG ELECTRO-MECHANICS COMPANY, LTD.
    Inventors: Kwan-Woo Kim, Kyutae Lim, Chang-Ho Lee, Haksun Kim, Joy Laskar
  • Publication number: 20100073084
    Abstract: Systems and methods may be provided for a LINC system having a level-shifting LINC amplifier. The systems and methods may include a dynamic power supply that is adjustable to provide at least a first voltage supply level and a second voltage supply level higher than the first voltage supply level; a first power amplifier that amplifies a first component signal to generate a first amplified signal; a second power amplifier that amplifiers a second component signal to generate a second amplified signal, where the first component signal and the second component signal are components of an original signal, where the first component signal and the second component signal each have a constant envelope, and where the original signal has a non-constant envelope, and where the first and second power amplifiers are biased at the first voltage supply level or the second voltage supply level based upon an analysis of an amplitude of the original signal.
    Type: Application
    Filed: September 21, 2009
    Publication date: March 25, 2010
    Applicant: SAMSUNG ELECTRO-MECHANICS COMPANY, LTD.
    Inventors: Joonhoi Hur, Kwan-Woo Kim, Kyutae Lim, Chang-Ho Lee, Haksun Kim, Joy Laskar
  • Patent number: 7675365
    Abstract: Systems and methods may be provided for a power amplifier system. The systems and methods may include a plurality of power amplifiers, where each power amplifier includes at least one output port. The systems and methods may also include a plurality of primary windings each having a first number of turns, where each primary winding is connected to at least one output port of the plurality of power amplifiers, and a single secondary winding inductively coupled to the plurality of primary windings, where the secondary winding includes a second number of turns greater than the first number of turns.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: March 9, 2010
    Assignees: Samsung Electro-Mechanics, Georgia Tech Research Corporation
    Inventors: Chang-Ho Lee, Kyu Hwan An, Ki Seok Yang, Jaejoon Chang, Wangmyong Woo, Younsuk Kim, Haksun Kim, Ockgoo Lee, Dong Ho Lee, Hyungwook Kim, Joy Laskar
  • Patent number: 7642858
    Abstract: Example embodiments of the invention may provide for active baluns. An example active balun may include a resonator that may convert a single-ended input signal to at least two differential input signals, and a differential switching block that includes first and second transistors that each receive a respective one of the at least two differential input signals from the resonator, where the first and second transistors may be cross-coupled to each other to provide a first differential output signal and a second differential output signal. An example active balun may further include one or more loads connected to the first and second differential output signals, and one or more stacked inverters that may provide a first output port and a second output port, where the first output port may be responsive to the first differential output signal and the second output port may be responsive to the second differential output signal.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: January 5, 2010
    Assignees: Samsung Electro-Mechanics Company, Georgia Tech Research Corporation
    Inventors: Dong Ho Lee, Ki Seok Yang, Yunseok Kim, Sanghee Kim, Hyogeun Bae, Kijoong Kim, Li Lee, Songcheol Hong, Chang-Ho Lee, Haksun Kim, Joy Laskar
  • Patent number: 7595700
    Abstract: Embodiments of the invention may provide for an LC quadrature oscillator that includes two LC oscillators that are cross-coupled with each other to generate I/Q clock signals and a phase and amplitude mismatch compensator. The phase and amplitude mismatch detector may include an amplitude mismatch detector, a transconductor, and a capacitor for compensating for both phase and amplitude mismatches between I/Q clock signals generated in the LC quadrature oscillator.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: September 29, 2009
    Assignees: Samsung Electro-Mechanics, Georgia Tech Research Corporation
    Inventors: Sangjin Byun, Chang-Ho Lee, Haksun Kim, Joy Laskar
  • Patent number: 7593704
    Abstract: The present invention describes a receiver assembly for receiving an analog signal and converting the analog signal to a digital signal. The receiver assembly is, preferably, capable of receiving a signal operating at approximately 60 GHz. The receiver assembly includes a filter, a down converter, a demodulator, a latch, a FIFO, and a logic circuit. A method of converting the 60 GHz analog signal to a digital signal is also described.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: September 22, 2009
    Assignee: Georgia Tech Research Corporation
    Inventors: Stephane Pinel, Joy Laskar
  • Patent number: 7576607
    Abstract: Embodiments of the invention may provide for power amplifier systems and methods. The systems and methods may include a power amplifier that generates a first differential output signal and a second differential output signal, a primary winding comprised of a plurality of primary segments, where a first end of each primary segment is connected to a first common input port and a second end of each primary segment is connected to a second common input port, where the first common input port is operative to receive the first differential output signal, and where the second common input port is operative to receive the second differential output signal, and a single secondary winding inductively coupled to the plurality of primary segments.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: August 18, 2009
    Assignees: Samsung Electro-Mechanics, Georgia Tech Research Corporation
    Inventors: Chang-Ho Lee, Ockgoo Lee, Jeonghu Han, Kyu Hwan An, Hyungwook Kim, Dong Ho Lee, Ki Seok Yang, Haksun Kim, Joy Laskar
  • Publication number: 20090184786
    Abstract: Embodiments of the invention may provide for power amplifier systems and methods. The systems and methods may include a power amplifier that generates a first differential output signal and a second differential output signal, a primary winding comprised of a plurality of primary segments, where a first end of each primary segment is connected to a first common input port and a second end of each primary segment is connected to a second common input port, where the first common input port is operative to receive the first differential output signal, and where the second common input port is operative to receive the second differential output signal, and a single secondary winding inductively coupled to the plurality of primary segments.
    Type: Application
    Filed: April 1, 2009
    Publication date: July 23, 2009
    Inventors: Chang-Ho Lee, Ockgoo Lee, Jeonghu Han, Kyu Hwan An, Hyungwook Kim, Dong Ho Lee, Ki Seok Yang, Haksun Kim, Joy Laskar
  • Patent number: 7560994
    Abstract: Example embodiments of the invention may provide systems and methods for a power amplifier. The systems and methods may include a first common-source device having a first source, a first gate, a first drain, and a first body, where the first source is connected to the first body, and wherein the first gate is connected to an input port. The systems and methods may further include a second common-gate device having a second source, a second gate, a second drain, and a second body, where the second source is connected to the first drain, where the second source is further connected to the second body, and where the second drain is connected to an output port.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: July 14, 2009
    Assignees: Samsung Electro-Mechanics Company, Georgia Tech Research Corporation
    Inventors: Ockgoo Lee, Jeonghu Han, Kyu Hwan An, Hyungwook Kim, Dong Ho Lee, Ki Seok Yang, Chang-Ho Lee, Haksun Kim, Joy Laskar
  • Publication number: 20090174477
    Abstract: Embodiments of the invention may provide for power amplifier systems and methods. The systems and methods may include a power amplifier that generates a first differential output signal and a second differential output signal, a primary winding comprised of a plurality of primary segments, where a first end of each primary segment is connected to a first common input port and a second end of each primary segment is connected to a second common input port, where the first common input port is operative to receive the first differential output signal, and where the second common input port is operative to receive the second differential output signal, and a single secondary winding inductively coupled to the plurality of primary segments.
    Type: Application
    Filed: January 3, 2008
    Publication date: July 9, 2009
    Inventors: Chang-Ho Lee, Ockgoo Lee, Jeonghu Han, Kyu Hwan An, Hyungwook Kim, Dong Ho Lee, Ki Seok Yang, Haksun Kim, Joy Laskar
  • Publication number: 20090174515
    Abstract: Example embodiments of the invention may provide systems and methods for multiple transformers. The systems and methods may include a first transformer that may include a first primary winding and a first secondary winding, where the first primary winding may be inductively coupled to the first secondary winding, where the first transformer may be associated with a first rotational current flow direction in the first primary winding.
    Type: Application
    Filed: January 8, 2008
    Publication date: July 9, 2009
    Inventors: Dong Ho Lee, Ki Seok Yang, Chang-Ho Lee, Haksun Kim, Joy Laskar
  • Publication number: 20090174480
    Abstract: Example embodiments of the invention may provide systems and methods for a power amplifier. The systems and methods may include a first common-source device having a first source, a first gate, a first drain, and a first body, where the first source is connected to the first body, and wherein the first gate is connected to an input port. The systems and methods may further include a second common-gate device having a second source, a second gate, a second drain, and a second body, where the second source is connected to the first drain, where the second source is further connected to the second body, and where the second drain is connected to an output port.
    Type: Application
    Filed: January 3, 2008
    Publication date: July 9, 2009
    Inventors: Ockgoo Lee, Jeonghu Han, Kyu Hwan An, Hyungwook Kim, Dong Ho Lee, Ki Seok Yang, Chang-Ho Lee, Haksun Kim, Joy Laskar
  • Publication number: 20090170438
    Abstract: Signals propagating on an aggressor communication channel can cause interference in a victim communication channel. A sensor coupled to the aggressor channel can obtain a sample of the aggressor signal. The sensor can be integrated with or embedded in a system, such as a flex circuit or a circuit board, that comprises the aggressor channel. The sensor can comprise a dedicated conductor or circuit trace that is near an aggressor conductor, a victim conductor, or an EM field associated with the interference. An interference compensation circuit can receive the sample from the sensor. The interference compensation circuit can have at least two operational modes of operation. In the first mode, the circuit can actively generate or output a compensation signal that cancels, corrects, or suppresses the interference. The second mode can be a standby, idle, power-saving, passive, or sleep mode.
    Type: Application
    Filed: March 2, 2009
    Publication date: July 2, 2009
    Inventors: Edward Gebara, Andrew Joo Kim, Joy Laskar, Anthony Stelliga, Emmanouil M. Tentzeris
  • Publication number: 20090140784
    Abstract: A first system and method relates to an analog current-mode method using branch systems. In the analog current-mode implementation, multiple branches systems can be scaled according to filter coefficients and switched using known data points. Positive coefficients can add current to the summing node, while negative coefficients can remove current from the summing node. Switches can be implemented with quick charge/discharge paths in order to operate at very high data rates. A second system and method relates to a digital look-up table based high-speed implementation. In the digital implementation, outputs can be pre-calculated as an n-bit output word that drives an n-bit DAC. Each bit of the n-bit word can then described as an independent function of the known data points. Each such function can be implemented as a high-speed combinational logic block. Both systems and methods enable the implementation of pulse shaping filters for multi-gigabit per second data transmission.
    Type: Application
    Filed: December 3, 2008
    Publication date: June 4, 2009
    Applicant: Georgia Tech Research Corporation
    Inventors: Bevin George PERUMANA, Arun Rachamadugu, Stephane Pinel, Joy Laskar
  • Patent number: 7528751
    Abstract: Embodiments of the invention may provide for a long delay generator for the spectrum sensing of cognitive radio systems. The long delay generator may include an Analog-to-Digital Converter (ADC), memory element, and Digital-to-Analog Converter (DAC). The memory element may utilize shift register bank or Random-Access Memory (RAM) cells. The long delay generator may provide for a selectable delay by digitizing the received signal, delaying the received signal in the digital domain, and reconstructing the delayed signal as an analog. The analog delayed signal may then be compared or otherwise correlated with the original input signal using an analog auto-correlation technique to determine whether a meaningful signal type has been identified or otherwise detected.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: May 5, 2009
    Assignees: Samsung Electro-Mechanics, Georgia Tech Research Corporation
    Inventors: Jongmin Park, Taejoong Song, Kyutae Lim, Chang-Ho Lee, Jeongsuk Lee, Kihong Kim, Seongsoo Lee, Haksun Kim, Joy Laskar
  • Patent number: 7522883
    Abstract: Signals propagating on an aggressor communication channel can cause interference in a victim communication channel. A sensor coupled to the aggressor channel can obtain a sample of the aggressor signal. The sensor can be integrated with or embedded in a system, such as a flex circuit or a circuit board, that comprises the aggressor channel. The sensor can comprise a dedicated conductor or circuit trace that is near an aggressor conductor, a victim conductor, or an EM field associated with the interference. An interference compensation circuit can receive the sample from the sensor. The interference compensation circuit can have at least two operational modes of operation. In the first mode, the circuit can actively generate or output a compensation signal that cancels, corrects, or suppresses the interference. The second mode can be a standby, idle, power-saving, passive, or sleep mode.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: April 21, 2009
    Assignee: Quellan, Inc.
    Inventors: Edward Gebara, Andrew Joo Kim, Joy Laskar, Anthony Stelliga, Emmanouil M. Tentzeris