Abstract: Signals propagating on an aggressor communication channel can cause interference in a victim communication channel. A sensor coupled to the aggressor channel can obtain a sample of the aggressor signal. The sensor can be integrated with or embedded in a system, such as a flex circuit or a circuit board, that comprises the aggressor channel. The sensor can comprise a dedicated conductor or circuit trace that is near an aggressor conductor, a victim conductor, or an EM field associated with the interference. An interference compensation circuit can receive the sample from the sensor. The interference compensation circuit can have at least two operational modes of operation. In the first mode, the circuit can actively generate or output a compensation signal that cancels, corrects, or suppresses the interference. The second mode can be a standby, idle, power-saving, passive, or sleep mode.

Abstract: A first system and method relates to an analog current-mode method using branch systems. In the analog current-mode implementation, multiple branches systems can be scaled according to filter coefficients and switched using known data points. Positive coefficients can add current to the summing node, while negative coefficients can remove current from the summing node. Switches can be implemented with quick charge/discharge paths in order to operate at very high data rates. A second system and method relates to a digital look-up table based high-speed implementation. In the digital implementation, outputs can be pre-calculated as an n-bit output word that drives an n-bit DAC. Each bit of the n-bit word can then described as an independent function of the known data points. Each such function can be implemented as a high-speed combinational logic block. Both systems and methods enable the implementation of pulse shaping filters for multi-gigabit per second data transmission.

Abstract: Embodiments of the invention may provide for a long delay generator for the spectrum sensing of cognitive radio systems. The long delay generator may include an Analog-to-Digital Converter (ADC), memory element, and Digital-to-Analog Converter (DAC). The memory element may utilize shift register bank or Random-Access Memory (RAM) cells. The long delay generator may provide for a selectable delay by digitizing the received signal, delaying the received signal in the digital domain, and reconstructing the delayed signal as an analog. The analog delayed signal may then be compared or otherwise correlated with the original input signal using an analog auto-correlation technique to determine whether a meaningful signal type has been identified or otherwise detected.

Abstract: Signals propagating on an aggressor communication channel can cause interference in a victim communication channel. A sensor coupled to the aggressor channel can obtain a sample of the aggressor signal. The sensor can be integrated with or embedded in a system, such as a flex circuit or a circuit board, that comprises the aggressor channel. The sensor can comprise a dedicated conductor or circuit trace that is near an aggressor conductor, a victim conductor, or an EM field associated with the interference. An interference compensation circuit can receive the sample from the sensor. The interference compensation circuit can have at least two operational modes of operation. In the first mode, the circuit can actively generate or output a compensation signal that cancels, corrects, or suppresses the interference. The second mode can be a standby, idle, power-saving, passive, or sleep mode.

Abstract: Embodiments of the invention may provide for an LC quadrature oscillator that includes two LC oscillators that are cross-coupled with each other to generate I/Q clock signals and a phase and amplitude mismatch compensator. The phase and amplitude mismatch detector may include an amplitude mismatch detectors a transconductor, and a capacitor for compensating for both phase and amplitude mismatches between I/Q clock signals generated in the LC quadrature oscillator.

Abstract: Embodiments of the invention may provide for a CMOS antenna switch, which may be referred to as a CMOS SPDT switch. The CMOS antenna switch may operate at a plurality of frequencies, perhaps around 900 MHz, 1.9 GHz and 2.1 GHz according to an embodiment of the invention. The CMOS antenna switch may include both a receiver switch and a transmit switch. The receiver switch may utilize a multi-stack transistor with body substrate switching and attachment of external capacitor between drain and gate to block high power signals from the transmit path as well as to maintain low insertion loss at the receiver path. Exemplary embodiments of the CMOS antenna switch may provide for 38 dBm P 0.1 dB at multi bands (e.g., 900 MHz, 1.8 GHz, and 2.1 GHz). In addition, ?60 dBc second and third harmonic performance up to 30 dBm input, may be obtained according to example embodiments of the invention.

Abstract: Embodiments of the invention may provide for a digital LINC (linear amplification with nonlinear components) transmitter. The digital LINC transmitter may include a signal component separator, at least one digital delay modulator, a frequency synthesizer, at least one power amplifier, a power combiner, an antenna, and a mismatch compensator. Additionally, systems and methods may be provided for compensating for phase and amplitude mismatches between two signal paths.

Abstract: Disclosed is a gain boosting technique for use with millimeter-wave cascode amplifiers. The exemplary technique may be implemented using a 0.18 ?m SiGe process (FT=140 GHz). It has also been shown that the technique is effective for CMOS processes with comparable FT. An exemplary gain-enhanced cascode stage was measured to have higher than 9 dB gain with a 1-dB bandwidth above 6 GHz with a DC power consumption of 13 mW. In addition, one cascode stage without gain boosting may be cascaded with two gain-boosted cascode amplifier stages to implement a three-stage LNA. The measured stable gain is higher than 24 dB at 60 GHz with a 3-dB bandwidth of 3.1 GHz for 25 mW of DC power consumption. It is believed that this is the first 60 GHz LNA with a higher than 20 dB gain using a 0.18 ?m SiGe process.

Abstract: Embodiments of the invention may provide for digital wavelet generators utilized in providing flexible spectrum-sensing resolutions for a Multi-Resolution Spectrum Sensing (MRSS) technique. Embodiments of the invention may provide for either multi-point or multi-rate digital wavelet generators. These digital wavelet generators may utilizing the same hardware resource optimally, and the various wavelet bases may be generated by changing the memory addressing schemes or clock speeds.

Abstract: An apparatus for generating an in-phase/quadrature-phase (I/Q) signal in a wireless transceiver is disclosed, including a local oscillator for generating an oscillation signal, and first and second mixers for mixing an oscillation signal with a transmission/reception signal to convert the transmission/reception signal into a baseband or high-frequency signal. The apparatus includes a phase locked circuit for controlling the local oscillator, and a polyphase filter installed between the local oscillator and the mixers, for separating the oscillation signal from the local oscillator into an I signal and a Q signal depending on a control signal from the phase locked circuit, and outputting the separated I and Q signals to the first and second mixers, respectively.

Abstract: Provided is a mixer for use in a direct conversion receiver. The mixer includes Field Effect Transistors (FETs), a current source (IBias), two load resistors (RLoad), another FET, and two inductors L1 and L2. The FET M21 constitutes a current bleeding circuitry and the other components except for the two inductors L1 and L2 constitute a so-called Gilbert cell mixer.

Abstract: Example embodiments of the invention may provide for active baluns. An example active balun may include a resonator that may convert a single-ended input signal to at least two differential input signals, and a differential switching block that includes first and second transistors that each receive a respective one of the at least two differential input signals from the resonator, where the first and second transistors may be cross-coupled to each other to provide a first differential output signal and a second differential output signal. An example active balun may further include one or more loads connected to the first and second differential output signals, and one or more stacked inverters that may provide a first output port and a second output port, where the first output port may be responsive to the first differential output signal and the second output port may be responsive to the second differential output signal.

Abstract: Systems and methods may be provided for threshold determinations for spectrum sensing. The systems and methods may include receiving a false alarm rate, where the false alarm rate is associated with false occupancy identifications of a spectrum segment, determining a noise floor as a function of a noise figure and characteristics of a multi-resolution spectrum sensing (MRSS) window, and calculating a sensing threshold based at least in part upon the false alarm rate and the noise floor. The systems and methods may also include determining whether a portion of an RF spectrum is occupied based at least in part on the calculated sensing threshold.

Abstract: Disclosed is an ultra wide band signal generator. The ultra wide band signal generator generates a signal of a required frequency using a harmonic signal having a frequency range of a ultra wide band (UWB). The ultra wide band signal generator includes an active inductor for generating harmonic signals having power strengths substantially equal to each other within a non-linear operation range, the tunable active inductor capable of tuning a value thereof, an oscillator for amplifying and outputting the harmonic signals generated from the active inductor by frequency-transiting the harmonic signals into high frequency bands, and a filter for selectively outputting one of the harmonic signals output from the oscillator.

Abstract: Systems and methods may be provided for a power amplifier system. The systems and methods may include a plurality of power amplifiers, where each power amplifier includes at least one output port. The systems and methods may also include a plurality of primary windings each having a first number of turns, where each primary winding is connected to at least one output port of the plurality of power amplifiers, and a single secondary winding inductively coupled to the plurality of primary windings, where the secondary winding includes a second number of turns greater than the first number of turns.

Abstract: A wireless communication system can comprise two or more antennas that interfere with one another via free space coupling, surface wave crosstalk, dielectric leakage, or other interference effect. The interference effect can produce an interference signal on one of the antennas. A cancellation device can suppress antenna interference by generating an estimate of the interference signal and subtracting the estimate from the interference signal. The cancellation device can generate the estimate based on sampling signals on an antenna that generates the interference or on an antenna that receives the interference. The cancellation device can comprise a model of the crosstalk effect. Transmitting test signals on the communication system can define or refine the model.

Abstract: Embodiments of the invention may provide for a CMOS antenna switch, which may be referred to as a CMOS SPDT switch. The CMOS antenna switch may operate at a plurality of frequencies, perhaps around 900 MHz 1.9 GHz and 2.1 GHz according to an embodiment of the invention. The CMOS antenna switch may include both a receiver switch and a transmit switch. The receiver switch may utilize a multi-stack transistor with body substrate switching and source and body connection along with body floating technique to block high power signals from the transmit path by preventing channel formation of the device in OFF state as well as to maintain low insertion loss at the receiver path. Example embodiments of the CMOS antenna switch may provide for 35 dBm P 1 dB at both bands (e.g., 900 MHz and 1.9 GHz and 2.1 GHz). In addition, a ?60 dBc second and third harmonic up to 28 dBm input power to the switch, may be obtained according to example embodiments of the invention.

Abstract: A wireless communication system can comprise two or more antennas that interfere with one another via free space coupling, surface wave crosstalk, dielectric leakage, or other interference effect. The interference effect can produce an interference signal on one of the antennas. A cancellation device can suppress antenna interference by generating an estimate of the interference signal and subtracting the estimate from the interference signal. The cancellation device can generate the estimate based on sampling signals on an antenna that generates the interference or on an antenna that receives the interference. The cancellation device can comprise a model of the crosstalk effect. Transmitting test signals on the communication system can define or refine the model.

Abstract: Embodiments of the invention may provide for a load regulation tuner that reduces the load regulation effect. The load regulation tuner may include a load current controlled current source that is responsive to a load current from a power transistor of a linear regulator, where the load current controlled current source includes a sensing transistor that generates a fraction of the load current as a sensed partial load current. The load regulation tuner may also include a resistor in parallel with a load current controlled current source, and where the paralleled resistor and the load current controlled current source form at least a portion of a feedback block that adjusts an operation of the linear regulator to provide a substantially constant load voltage.

Abstract: Embodiments of the invention may provide for a CMOS antenna switch, which may be referred to as a CMOS SP4T switch. The CMOS antenna switch may operate at a plurality of frequencies, perhaps around 900 MHz and 1.9 GHz according to an embodiment of the invention. The CMOS antenna switch may include both a receiver switch and a transmit switch. The receiver switch may utilize a multi-stack transistor with body substrate tuning to block high power signals from the transmit path as well as to maintain low insertion loss at the receiver path. On the other hand, in the transmit switch, a body substrate tuning technique may be applied to maintain high power delivery to the antenna. Example embodiments of the CMOS antenna switch may provide for 31 dBm P 1 dB at both bands (e.g., 900 MHz and 1.8 GHz). In addition, a 0.9 dB and ?1.1 dB insertion loss at 900 MHz and 1.9 GHz, respectively, may be obtained according to example embodiments of the invention.