Abstract: A tunable capacitor device may be provided in accordance with example embodiments of the invention. The tunable capacitor device may include a first capacitor; a second capacitor; a third capacitor, where the first, second, and third capacitors are connected in series, wherein the second capacitor is positioned between the first capacitor and the second capacitor; and at least one switch transistor, where the at least one switch transistor is connected in parallel with the second capacitor.

Abstract: Systems and methods are provided for power amplifiers with discrete power control. The systems and methods may include a plurality of unit power amplifiers; a plurality of primary windings, wherein each primary winding is connected to at least one respective output port of a respective one the plurality of unit power amplifiers; a secondary winding inductively coupled to the plurality of primary windings, where the secondary winding provides an overall output; a bias controller, where the bias controller provides a respective bias voltage based at least in part on a level of output power to one or more of the plurality of unit power amplifiers; and a switch controller, where the switch controller operates to activate or deactivate at least one of the plurality of unit power amplifiers via a respective control signal.

Abstract: A method of fabricating an ultra-high frequency module is disclosed. The method includes providing a top layer; drilling the top layer; milling the top layer; providing a bottom; milling the bottom layer to define a bottom layer cavity; aligning the top layer and the bottom layer; and adhering the top layer to the bottom layer. The present invention also includes an ultra-high frequency module operating at ultra-high speeds having a top layer, the top layer defining a top layer cavity; a bottom layer, the bottom layer defining a bottom layer cavity; and an adhesive adhering both the top layer to the bottom layer, wherein the top layer and the bottom layer are formed from a large area panel of a printed circuit board.

Abstract: Systems and methods for providing an adaptive bias circuit that may include a differential amplifier, low-pass filter, and common source amplifier or common emitter amplifier. The adaptive bias circuit may generate an adaptive bias output signal depending on input signal power level. As the input power level goes up, the adaptive bias circuit may increase the bias voltage or bias current of the adaptive bias output signal. A power amplifier (e.g., a differential amplifier) may be biased according to the adaptive bias output signal in order to reduce current consumption at low power operation levels.

Abstract: A system for a power transmitter may be provided. The system may include a first amplifier stage having at least a first transistor and a second transistor that are connected in a first cascode configuration; a second amplifier stage having at least a third transistor and a fourth transistor that are connected in a second cascode configuration, where the first transistor receives a system input of the power transmitter, where the second transistor is connected to the third transistor, and where the fourth transistor provides a system output of the power transmitter; and a feedback network that connects a first gate or base of the fourth transistor with a second gate or base of the second transistor.

Abstract: A multi-primary and distributed transformer is provided for one or more sets of parallel-connected or series-connected power amplifiers. The transformer may include a plurality of primary windings, including a first primary winding, a second primary winding, a third primary winding, and a fourth primary winding, where each of the plurality of primary windings is not directly connected to any other of the plurality of primary windings, where each primary winding includes a respective positive port and a negative port for receiving respective differential signals, where each primary winding include a respective first number of turns; and a single secondary winding having a plurality of segments, including a first segment and a second segment, where each segment includes a second number of turns, the second number of turns greater than or equal to the respective first number of turns, where the single secondary winding includes at least one output port.

Abstract: Embodiments of the invention may provide for power amplifier systems and methods. The systems and methods may include a power amplifier that generates a first differential output signal and a second differential output signal, a primary winding comprised of a plurality of primary segments, where a first end of each primary segment is connected to a first common input port and a second end of each primary segment is connected to a second common input port, where the first common input port is operative to receive the first differential output signal, and where the second common input port is operative to receive the second differential output signal, and a single secondary winding inductively coupled to the plurality of primary segments.

Abstract: A SPDT or SPMT switch may include a transformer having a primary winding and a secondary winding, where a first end of the secondary winding is connected to a single pole port, where a first end of the primary winding is connected to a first throw port; a first switch having a first end and a second end, where the first end is connected to ground; and a second switch, where a second end of the secondary winding is connected to both a second end of the first switch and a first end of the second switch, where a second end of the second switch is connected to a second throw port, where the first switch controls a first communication path between the single pole port and the first throw port, and where the second switch controls a second communication path between the second throw port and the single pole port.

Abstract: Embodiments of the invention may provide for a digital LINC (linear amplification with nonlinear components) transmitter. The digital LINC transmitter may include a signal component separator, at least one digital delay modulator, a frequency synthesizer, at least one power amplifier, a power combiner, an antenna, and a mismatch compensator. Additionally, systems and methods may be provided for compensating for phase and amplitude mismatches between two signal paths.

Abstract: Embodiments of the invention may provide for a CMOS antenna switch, which may be referred to as a CMOS SP4T switch. The CMOS antenna switch may operate at a plurality of frequencies, perhaps around 900 MHz and 1.9 GHz according to an embodiment of the invention. The CMOS antenna switch may include both a receiver switch and a transmit switch. The receiver switch may utilize a multi-stack transistor with body substrate tuning to block high power signals from the transmit path as well as to maintain low insertion loss at the receiver path. On the other hand, in the transmit switch, a body substrate tuning technique may be applied to maintain high power delivery to the antenna. Example embodiments of the CMOS antenna switch may provide for 31 dBm P 1 dB at both bands (e.g., 900 MHz and 1.8 GHz). In addition, a 0.9 dB and ?1.1 dB insertion loss at 900 MHz and 1.9 GHz, respectively, may be obtained according to example embodiments of the invention.

Abstract: Systems and methods may be provided for a power amplifier system. The systems and methods may include a plurality of power amplifiers, where each power amplifier includes at least one output port. The systems and methods may also include a plurality of primary windings each having a first number of turns, where each primary winding is connected to at least one output port of the plurality of power amplifiers, and a single secondary winding inductively coupled to the plurality of primary windings, where the secondary winding includes a second number of turns greater than the first number of turns.

Abstract: A method of fabricating an ultra-high frequency module is disclosed. The method includes providing a top layer; drilling the top layer; milling the top layer; providing a bottom; milling the bottom layer to define a bottom layer cavity; aligning the top layer and the bottom layer; and adhering the top layer to the bottom layer. The present invention also includes an ultra-high frequency module operating at ultra-high speeds having a top layer, the top layer defining a top layer cavity; a bottom layer, the bottom layer defining a bottom layer cavity; and an adhesive adhering both the top layer to the bottom layer, wherein the top layer and the bottom layer are formed from a large area panel of a printed circuit board.

Abstract: Embodiments of the invention may provide for a CMOS antenna switch, which may be referred to as a CMOS SPDT switch. The CMOS antenna switch may operate at a plurality of frequencies, perhaps around 900 MHz 1.9 GHz and 2.1 GHz according to an embodiment of the invention. The CMOS antenna switch may include both a receiver switch and a transmit switch. The receiver switch may utilize a multi-stack transistor with body substrate switching and source and body connection along with body floating technique to block high power signals from the transmit path by preventing channel formation of the device in OFF state as well as to maintain low insertion loss at the receiver path. Example embodiments of the CMOS antenna switch may provide for 35 dBm P 1 dB at both bands (e.g., 900 MHz and 1.9 GHz and 2.1 GHz). In addition, a ?60 dBc second and third harmonic up to 28 dBm input power to the switch, may be obtained according to example embodiments of the invention.

Abstract: Example embodiments of the invention may provide systems and methods for multiple transformers. The systems and methods may include a first transformer that may include a first primary winding and a first secondary winding, where the first primary winding may be inductively coupled to the first secondary winding, where the first transformer may be associated with a first rotational current flow direction in the first primary winding.

Abstract: A voltage controlled oscillator-phase lock loop (VCO-PLL) system includes a voltage controlled oscillator (VCO) system implementing four-channel architecture, such that two bands support two channels; a phase-locked-loop (PLL) system; and a mixer system. The VCO system further includes a control circuit; a first cross-coupled oscillator system adapted to receive a source voltage; a second cross-coupled oscillator system adapted to receive the source voltage; and a plurality of isolation buffer systems adapted to protect the first and second cross-coupled oscillator systems.

Abstract: Embodiments of the invention may provide for a load regulation tuner that reduces the load regulation effect. The load regulation tuner may include a load current controlled current source that is responsive to a load current from a power transistor of a linear regulator, where the load current controlled current source includes a sensing transistor that generates a fraction of the load current as a sensed partial load current. The load regulation tuner may also include a resistor in parallel with a load current controlled current source, and where the paralleled resistor and the load current controlled current source form at least a portion of a feedback block that adjusts an operation of the linear regulator to provide a substantially constant load voltage.

Abstract: Signals propagating on an aggressor communication channel can cause detrimental interference in a victim communication channel. A signal processing circuit can generate an interference cancellation signal that, when applied to the victim communication channel, cancels the detrimental interference. The signal processing circuit can dynamically adjust or update two or more aspects of the interference cancellation signal, such as an amplitude or gain parameter and a phase or delay parameter. Via the dynamic adjustments, the signal processing circuit can adapt to changing conditions, thereby maintaining an acceptable level of interference cancellation in a fluctuating operating environment. A control circuit that implements the parametric adjustments can have at least two modes of operation, one for adjusting the amplitude parameter and one for adjusting the phase parameter. The modes can be selectable or can be intermittently available, for example.

Abstract: Systems and methods may be provided for threshold determinations for spectrum sensing. The systems and methods may include receiving a false alarm rate, where the false alarm rate is associated with false occupancy identifications of a spectrum segment, determining a noise floor as a function of a noise figure and characteristics of a multi-resolution spectrum sensing (MRSS) window, and calculating a sensing threshold based at least in part upon the false alarm rate and the noise floor. The systems and methods may also include determining whether a portion of an RF spectrum is occupied based at least in part on the calculated sensing threshold.

Abstract: Systems and methods for providing a self-mixing adaptive bias circuit that may include a mixer, low-pass filter or a phase shifter, and a bias feeding block. The self-mixing adaptive bias circuit may generate an adaptive bias signal depending on input signal power level. As the input power level goes up, the adaptive bias circuit increases the bias voltage or bias current such that the amplifier will save current consumption at low power operation levels and obtain better linearity at high power operation levels compared to conventional biasing techniques. Moreover, the adaptive bias output signal can be used to cancel the third-order intermodulation terms (IM3) to further enhance the linearity as a secondary effect.

Abstract: Systems and methods may be provided for a power amplifier system. The systems and methods may include a plurality of power amplifiers, where each power amplifier includes at least one output port. The systems and methods may also include a plurality of primary windings each having a first number of turns, where each primary winding is connected to at least one output port of the plurality of power amplifiers, and a single secondary winding inductively coupled to the plurality of primary windings, where the secondary winding includes a second number of turns greater than the first number of turns.