Patents by Inventor Jui Chang

Jui Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11956994
    Abstract: The present disclosure is generally related to 3D imaging capable OLED displays. A light field display comprises an array of 3D light field pixels, each of which comprises an array of corrugated OLED pixels, a metasurface layer disposed adjacent to the array of 3D light field pixels, and a plurality of median layers disposed between the metasurface layer and the corrugated OLED pixels. Each of the corrugated OLED pixels comprises primary or non-primary color subpixels, and produces a different view of an image through the median layers to the metasurface to form a 3D image. The corrugated OLED pixels combined with a cavity effect reduce a divergence of emitted light to enable effective beam direction manipulation by the metasurface. The metasurface having a higher refractive index and a smaller filling factor enables the deflection and direction of the emitted light from the corrugated OLED pixels to be well controlled.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: April 9, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Chung-Chih Wu, Hoang Yan Lin, Guo-Dong Su, Zih-Rou Cyue, Li-Yu Yu, Wei-Kai Lee, Guan-Yu Chen, Chung-Chia Chen, Wan-Yu Lin, Gang Yu, Byung-Sung Kwak, Robert Jan Visser, Chi-Jui Chang
  • Patent number: 11951901
    Abstract: A display system suitable for a vehicle is provided. The display system suitable for the vehicle includes a center console, a processing device, and a display device. The center console is configured to generate a power sequence according to a customization setting, and the power sequence corresponds to content of a data table. The processing device is configured to receive the power sequence and decodes the power sequence through a lookup table to generate a decoding result. The lookup table includes the content of the data table. The display device is coupled to the processing device and is configured to display a display image according to the decoding result.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: April 9, 2024
    Assignee: Coretronic Corporation
    Inventors: Jui-Ta Liu, Wen-Chang Chien, Tsung-Hsin Yeh, Shao-Chi Lin
  • Publication number: 20240105879
    Abstract: A light-emitting diode and a manufacturing method thereof are provided. The manufacturing method includes following steps. First, an LED wafer is provided. The LED wafer includes a substrate and a light-emitting semiconductor stacking structure positioned on the surface of the substrate. The light-emitting semiconductor stacking structure includes a first type semiconductor layer, an active layer, and a second type semiconductor layer from a side of the substrate. Second, dicing lanes are defined on the upper surface of the LED wafer. Third, dicing is performed along the dicing lanes of the substrate using a laser. The laser is focused on the lower surface of the substrate to form a surface hole and focused inside the substrate to form an internal hole. The diameter of the surface hole is greater than the diameter of the internal hole. Fourth, the LED wafer is separated into LED chips along the dicing lanes.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 28, 2024
    Applicant: Quanzhou sanan semiconductor technology Co., Ltd.
    Inventors: TSUNG-MING LIN, CHUNG-YING CHANG, YI-JUI HUANG, YU-TSAI TENG
  • Publication number: 20240097005
    Abstract: Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a gate structure over a semiconductor substrate, having a high-k dielectric layer, a p-type work function layer, an n-type work function layer, a dielectric anti-reaction layer, and a glue layer; and a continuous metal cap over the gate structure formed by metal material being deposited over the gate structure, a portion of the anti-reaction layer being selectively removed, and additional metal material being deposited over the gate structure. A semiconductor fabrication method includes: receiving a gate structure; flattening the top layer of the gate structure; precleaning and pretreating the surface of the gate structure; depositing metal material over the gate structure to form a discontinuous metal cap; selectively removing a portion of the anti-reaction layer; depositing additional metal material over the gate structure to create a continuous metal cap; and containing growth of the metal cap.
    Type: Application
    Filed: January 12, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Hang Chiu, Jui-Yang Wu, Kuan-Ting Liu, Weng Chang
  • Publication number: 20240096849
    Abstract: A semiconductor structure includes a semiconductor die, a redistribution circuit structure, and a terminal. The redistribution circuit structure is disposed on and electrically coupled to the semiconductor die. The terminal is disposed on and electrically coupled to the redistribution circuit structure, where the redistribution circuit structure is disposed between the semiconductor die and the terminal, and the terminal includes an under-bump metallization (UBM) and a capping layer. The UBM is disposed on and electrically coupled to the redistribution circuit structure, where the UBM includes a recess. The capping layer is disposed on and electrically coupled to the UBM, where the UBM is between the capping layer and the redistribution circuit structure, and the capping layer fills the recess of the UBM.
    Type: Application
    Filed: January 9, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chung Chang, Ming-Che Ho, Hung-Jui Kuo
  • Publication number: 20240096895
    Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Jui-Chien Huang, Shih-Cheng Chen, Chih-Hao Wang, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Lo-Heng Chang, Shi Ning Ju, Guan-Lin Chen
  • Publication number: 20240085797
    Abstract: A method of controlling an extreme ultraviolet (EUV) lithography system is disclosed. The method includes irradiating a target droplet with EUV radiation, detecting EUV radiation reflected by the target droplet, determining aberration of the detected EUV radiation, determining a Zernike polynomial corresponding to the aberration, and performing a corrective action to reduce a shift in Zernike coefficients of the Zernike polynomial.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Ya CHENG, Han-Lung CHANG, Shi-Han SHANN, Li-Jui CHEN, Yen-Shuo SU
  • Patent number: 11930624
    Abstract: An electronic device protecting casing with heating function includes: a casing; a battery box within the casing; an interior of the battery box being arranged with a battery, a back side of the battery box being formed with an opening for receiving the battery; an outer cover serving to seal the opening; an inner side of the outer cover being formed with a heat isolation sheet; a heating unit being installed within the casing for heating the tablet computer; the heating unit including an electric heating plate. When power of the battery is transferred to the electric heating plate, the electric heating plate generates heat power and then transfers the power to the tablet computer for heating it; and a control circuit is installed within the casing; the electric heating plate is connected to the battery through a control switch; and the control circuit is connected to the control switch.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: March 12, 2024
    Assignee: THE JOY FACTORY, INC.
    Inventors: Sampson Yang, Yun-Chang Tsui, Jui-Lin Wu
  • Patent number: 11921164
    Abstract: A battery pack for an information handling system includes a battery cell configured to provide current to the information handling system, and a battery management unit including an output to the information handling system. The output provides a maximum continuous current (MCC) indication and a peak power (PP) indication. The battery management unit determines an amount of current that the battery cell provides to the information handling system and determines an optimum MCC value that the battery cell can provide to the information handling system. The battery management unit further provides a first value on the PP indication, the first value being greater than the optimum MCC value, sums the amount of current provided to the information handling system that is in excess of the optimum MCC value, determines that the sum is greater than a threshold, and provides a second value on the PP indication, the second value being less than the optimum MCC value.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: March 5, 2024
    Assignee: Dell Products L.P.
    Inventors: Wen-Yung Chang, Chin-Jui Liu, Chien-Hao Chiu
  • Publication number: 20240045316
    Abstract: An illumination system providing an illumination beam includes a light source module generating first to third color beams, a light splitting and combining element, a beam expanding and collimating module, a reflecting element, and a light combining module. The first and second color beams are reflected by the light splitting and combining element after being transmitted to the light splitting and combining element. Paths of the first and second color beams leaving the light splitting and combining element are coincident. The first and second color beams from the light splitting and combining element are expanded and collimated by the beam expanding and collimating module and transmitted to the light combining module. The third color beam is reflected by the reflecting element and transmitted to the light combining module. Paths of the first to third color beams after leaving the light combining module are coincident. A projection device is provided.
    Type: Application
    Filed: August 1, 2023
    Publication date: February 8, 2024
    Applicant: Coretronic Corporation
    Inventors: Jui Chang, Kuan-Ta Huang, Jo-Han Hsu
  • Publication number: 20240039165
    Abstract: An antenna is provided. The antenna includes a first radiator and a second radiator. The first radiator includes a first section and a second section. The first section includes a first grounding edge and a first bending edge. The second section is connected to the first bending edge. The first grounding edge is grounded. The first section is not parallel to the second section. A first slot is formed on the first section. The second radiator includes a third section and a fourth section. The third section includes a second grounding edge and a second bending edge. The fourth section is connected to the second bending edge. The second grounding edge is grounded. The third section is not parallel to the fourth section. The first section is parallel to the third section.
    Type: Application
    Filed: June 29, 2023
    Publication date: February 1, 2024
    Inventors: Hsuan-Jui CHANG, Nai-Chen LIU, Shih-Huang YEH, Chung-Hsin CHIANG, Wun-Jian LIN
  • Publication number: 20240035971
    Abstract: A fluorescence lifetime imaging microscopy system comprises a microscope comprising an excitation source configured to direct an excitation energy to an imaging target, and a detector configured to measure emissions of energy from the imaging target, and a non-transitory computer-readable medium with instructions stored thereon, which perform steps comprising collecting a quantity of measured emissions of energy from the imaging target as measured data, providing a trained neural network configured to calculate fluorescent decay parameters from the quantity of measured emissions of energy, providing the data to the trained neural network, and calculating at least one fluorescence lifetime parameter with the neural network from the measured data, wherein the measured data comprises an input fluorescence decay histogram, and wherein the neural network was trained by a generative adversarial network. A method of training a neural network and a method of acquiring an image are also described.
    Type: Application
    Filed: September 17, 2021
    Publication date: February 1, 2024
    Inventors: Hsin-Chih Yeh, Yuan-I Chen, Yin-Jui Chang, Shih-Chu Liao, Trung Duc Nguyen, Soonwoo Hong, Yu-An Kuo, Hsin-Chin Li
  • Publication number: 20240027884
    Abstract: An illumination system includes first to third reflection components, a first light splitting and combining element, and a lens. The first and second reflection components reflect a first color beam and another first color beam, respectively. The third reflection element reflects a second color beam and another second color beam. The first light splitting and combining element passes the second color beams and reflects the first color beams. The first color beams and the second color beams leaving the first light splitting and combining element respectively form first and second irradiation areas not overlapped with each other and third and fourth irradiation areas not overlapped with each other on the lens, and each of the first and second irradiation areas are overlapped with at least a portion of the third and fourth irradiation areas.
    Type: Application
    Filed: July 19, 2023
    Publication date: January 25, 2024
    Applicant: Coretronic Corporation
    Inventors: Jui Chang, Kuan-Ta Huang, Jo-Han Hsu
  • Publication number: 20240028386
    Abstract: Aspects of the present disclosure provide a method for controlling a processing device to execute an application that employs a neural network (NN). The processing device includes a plurality of processing units arranged in a network-on-chip (NoC) to which the NN is mapped. For example, the method can include obtaining compiler information. The compiler information can include computing loads of the application on the processing units. The computing loads can relate a dataflow type of the NN. The method can also include determining a scaling factor for computing time of each of the processing units based on the computing loads, adjusting the computing time of the processing units based on the scaling factors, and enabling the processing units to perform their respective tasks of the application within their respective adjusted computing time.
    Type: Application
    Filed: July 21, 2023
    Publication date: January 25, 2024
    Applicant: MEDIATEK INC.
    Inventors: En-Jui CHANG, Chih-Chung CHENG
  • Publication number: 20240028881
    Abstract: Aspects of the present disclosure provide a method for controlling a processing device to execute an application that runs on a neural network (NN). The processing device can include a plurality of processing units that are arranged in a network-on-chip (NoC) architecture. For example, the method can include obtaining compiler information relating the application and the NoC, controlling the processing device to employ a first routing scheme to process the application when the compiler information does not meet a predefined requirement, and controlling the processing device to employ a second routing scheme to process the application when the compiler information meets the predefined requirement.
    Type: Application
    Filed: July 21, 2023
    Publication date: January 25, 2024
    Applicant: MEDIATEK INC.
    Inventors: En-Jui CHANG, Chih-Chung CHENG
  • Publication number: 20240019760
    Abstract: An optical element driving mechanism is provided, including a movable part, a fixed part, and a driving assembly. The movable part is connected to an optical element. The movable part is movable relative to the fixed part. The driving assembly drives the movable part to move relative to the fixed par. The fixed part includes an outer frame and a base.
    Type: Application
    Filed: July 13, 2023
    Publication date: January 18, 2024
    Inventors: Chen-Hung CHAO, Po-Xiang ZHUANG, Yi-Ho CHEN, Shou-Jen LIU, Sin-Jhong SONG, Cheng-Jui CHANG
  • Publication number: 20240004474
    Abstract: A film deformation element includes a first stack and a second stack. The first stack includes a first passivation layer, a first substrate, a first metal layer and a first dielectric layer. The first substrate is disposed on the first passivation layer. The first metal layer is disposed on the first substrate. The first dielectric layer is disposed on the first metal layer. The second stack is bonded to the first stack, to form a sealing space. The second stack includes a second passivation layer, a second substrate, a second metal layer and a second dielectric layer. The second dielectric layer is disposed on and faces the first dielectric layer. The second metal layer is disposed on the second dielectric layer. The second substrate is disposed on the second metal layer. The second passivation layer is disposed on the second substrate.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 4, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Chen-Tsai Yang, Heng-Yin Chen, Wan-Chen Yang, Jui-Chang Chuang, Hung-Hsien Ko, Min-Hsiung Liang, Chih-Cheng Cheng
  • Publication number: 20230420640
    Abstract: Provided are an electrolytic copper foil, an electrode and a lithium-ion cell comprising the same. The electrolytic copper foil has a first surface and a second surface, which are analyzed by grazing incidence X-ray diffraction (GIXRD), and each have an intensity of a characteristic peak of (111) plane denoted by I1, an intensity of a characteristic peak of (200) plane denoted by I2, an intensity of a characteristic peak of (220) plane denoted by I3, an FWHM of the characteristic peak of (111) plane denoted by W1, and an FWHM of the characteristic peak of (200) plane denoted by W2. The first and second surfaces each have a ratio of (I1+I2)/(I1+I2+I3) of 0.83 or more and a value of (W1+W2) of 0.80 or less. By controlling the features, it can improve the corrosion resistance of the electrolytic copper foil and further increase the safety of the lithium-ion cell.
    Type: Application
    Filed: October 4, 2022
    Publication date: December 28, 2023
    Inventors: Chih-Chung WU, Yao-Sheng LAI, Jui-Chang CHOU
  • Publication number: 20230420688
    Abstract: Provided are an electrolytic copper foil, an electrode and a lithium-ion cell comprising the same. The electrolytic copper foil has a first surface and a second surface opposite the first surface. An absolute difference of the FWHM of the characteristic peaks of (111) planes of the first surface and the second surface analyzed by GIXRD is less than 0.14, the first and the second surfaces each have a nanoindentation hardness of 0.3 GPa to 3.0 GPa, and the yield strength of the electrolytic copper foil is more than 230 MPa. By controlling the absolute difference of the FWHM of the characteristic peaks of (111) plane of these two surfaces, the nanoindentation hardness of these two surfaces and the yield strength, the electrolytic copper foil can have improved tolerance to the repeated charging and discharging and reduced warpage, thereby improving the yield rate and value of the lithium-ion cell.
    Type: Application
    Filed: September 8, 2022
    Publication date: December 28, 2023
    Inventors: Ting-Mu CHUANG, SUNG-SHIUAN LIN, Yao-Sheng LAI, Jui-Chang CHOU
  • Patent number: 11854873
    Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu Lun Ke, Yi-Wei Chiu, Hung Jui Chang, Yu-Wei Kuo