Abstract: A surface-treated copper foil includes a bulk copper foil and a first surface treatment layer. The first surface treatment layer is disposed on a first surface of the bulk copper foil and includes a roughening layer, where the outermost surface of the first surface treatment layer is a treating surface of the surface-treated copper foil. The material volume (Vm) of the treating surface is 0.06 to 1.45 ?m3/?m2, and the five-point peak height (S5p) of the treating surface is 0.15 to 2.00 ?m.

Abstract: A beam splitter/combiner includes a first light-transmitting substrate, a first light transmission element, and a second light transmission element. The first light-transmitting substrate has a first optical surface facing incident light and a second optical surface opposite to the first optical surface. The first light transmission element is disposed on the first optical surface. The second light transmission element is disposed on the second optical surface. A first color beam incident on the first light-transmitting substrate is reflected by the first light transmission element and leaves the first light-transmitting substrate. A second color beam incident on the first light-transmitting substrate passes through the first light transmission element, is reflected by the second light transmission element, then passes through the first light transmission element, and leaves the first light-transmitting substrate.

Abstract: An electronic device and an antenna module are provided. The electronic device includes a metal housing with a slot having an open end and a first upper edge portion located at an upper edge of the slot. The antenna module is arranged in the metal housing and includes a carrier board, a feeding element, a radiating element with a feeding portion connected to the feeding element, and a first parasitic radiating element arranged on the carrier board and connected or coupled to the first upper edge portion. A vertical projection of the radiating element on the metal housing at least partially overlaps the slot. One side of the first parasitic radiating element is near an edge of the open end. The radiating element is fed with a signal through the feeding element to generate a resonant mode and is coupled to the slot to excite another resonant mode.

Abstract: Exemplary subpixel structures include a directional light-emitting diode structure characterized by a full-width-half-maximum (FWHM) of emitted light having a divergence angle of less than or about 10°. The subpixel structure further includes a lens positioned a first distance from the light-emitting diode structure, where the lens is shaped to focus the emitted light from the light-emitting diode structure. The subpixel structure still further includes a patterned light absorption barrier positioned a second distance from the lens. The patterned light absorption barrier defines an opening in the barrier, and the focal point of the light focused by the lens is positioned within the opening. The subpixels structures may be incorporated into a pixel structure, and pixel structures may be incorporated into a display that is free of a polarizer layer.

Abstract: A light-emitting pixel structure is described that may include a group of light-emitting diode structures, where each of the light-emitting diode structures is operable to emit light characterized by a different peak emission wavelength. The structures may also include a patterned light absorption barrier characterized by a group of openings in the barrier, where each of the openings permit a transmission of a portion of the light from one of the light-emitting diode structures through the barrier. The structures may further include a metasurface layer operable to change a direction of at least some of the light transmitted through the openings of the patterned light absorption barrier from the light-emitting diode structures.

Abstract: The method for removing partial metal wall of hole of the present invention includes the following steps. First, a circuit board is provided. The circuit board includes a plurality of circuit layers, a plurality of dielectric layers, and a plated through hole. Each of the dielectric layers is between two adjacent circuit layers. The wall of the plated through hole includes at least one residual copper. The circuit layer immediately below the residual copper is defined as a signal layer. Next, a position of the signal layer and a position of the residual copper in the plated through hole are obtained. Next, a drill is provided, the drill includes a main body and at least one needle, and the drill is moved to the position of the residual copper. The main body is rotated around the central axis of the main body, so the needle can remove part of the residual copper.

Abstract: A duty margin monitoring circuit, coupled to a functional circuit which generates a first output signal in response to a target signal, includes a modulation circuit, a replica circuit and an error detection circuit. The modulation circuit is arranged to receive the target signal and modulate the target signal to generate a modulated target signal. The replica circuit is arranged to receive the modulated target signal and generate a second output signal in response to the modulated target signal. The error detection circuit is coupled to the functional circuit and the replica circuit to receive the first output signal and the second output signal and arranged to generate an error detection result according to the first output signal and the second output signal.

Abstract: A package structure of a roll-shaped thin film includes a thin film roll and a buffer layer. The thin film roll includes a winding core and a thin film wound around the winding core, and the buffer layer is wound around an outer circumference of the thin film. An end portion of the buffer layer is covered with an inner surface of an end portion of the thin film, and the thickness of the buffer layer is in a range of 1-20 mm.

Abstract: A semiconductor package includes a substrate, a semiconductor die, a lid, and an adhesive layer. The semiconductor die is attached to the substrate. The lid is over the semiconductor die and the substrate. The adhesive layer is sandwiched between the lid and the semiconductor die. The adhesive layer includes a metallic thermal interface material (TIM) layer and a polymeric TIM layer adjacent to the metallic TIM layer. The polymeric TIM layer is located on corners of the semiconductor die from a top view.

Abstract: An electromagnetic measuring probe device for measuring a thickness of a dielectric layer of a circuit board and a method thereof are disclosed. The circuit board has at least one dielectric layer, at least two conductive layers and a test area. The test area has a test pattern and a through hole. The electromagnetic measuring probe device has a probe-measuring unit, an external conductive element, plural magnetic powder groups, and a maintaining unit. The probe-measuring unit has a transparent tube and an internal conductive pin. The external conductive element electrically connects with the test pattern. The conductive layers and the internal conductive pin generate a magnetic field while the probe-measuring unit enters into the through hole. The magnetic powder groups magnetically attracted are gathered to positions corresponding to thickness-range positions of the conductive layers and held by the maintaining unit, thus a gap between the two dielectric layers is obtained.

Abstract: A semiconductor device includes at least one active region, a first dielectric layer, a gate structure, and an air void. The active region includes a III-V compound semiconductor layer. The first dielectric layer is disposed on the active region. The gate structure is disposed on the active region, and at least a part of the gate structure is disposed in the first dielectric layer. The air void is disposed in the first dielectric layer, and at least a part of the air void is disposed at two opposite sides of the gate structure in a horizontal direction.

Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.

Abstract: Methods of forming semiconductor devices are provided. The methods include: forming a trench in a substrate, wherein the trench includes a defect protruding from a bottom surface of the trench; forming a flowable material on the substrate to at least partially cover the defect; performing an etching process to reduce the height of the defect; and removing the flowable material.

Abstract: A surface-treated copper foil includes a treated surface, where the peak extreme height (Sxp) of the treating surface is 0.4 to 3.0 ?m. When the surface-treated copper foil is heated at a temperature of 200° C. for 1 hour, the ratio of the integrated intensity of diffraction peak of (111) plane to the sum of the integrated intensities of diffraction peaks of (111) plane, (200) plane, and (220) plane of the treating surface is at least 60%.

Abstract: A surface-treated copper foil including a treating surface, where the root mean square height (Sq) of the treating surface is in a range of 0.20 to 1.50 ?m and the texture aspect ratio (Str) of the treating surface is not greater than 0.65. When the surface-treated copper foil is heated at a temperature of 200° C. for 1 hour, the ratio of the integrated intensity of (111) peak to the sum of the integrated intensities of (111) peak, (200) peak, and (220) peak of the treating surface is at least 60%.

Abstract: A device comprises a plurality of 2D semiconductor nanostructures, a gate structure, a source region, and a drain region. The plurality of 2D semiconductor nanostructures extend in a first direction above a substrate and arranged in a second direction substantially perpendicular to the first direction. The gate structure surrounds each of the plurality of 2D semiconductor nanostructures. The source region and the drain region are respectively on opposite sides of the gate structure.

Abstract: A physiological sensor device and system, and a correction method are provided. The physiological sensor device includes a physiological signal sensor, a first compensation sensor, and a signal processing device. The physiological signal sensor is attached to an object to be detected to sense a physiological signal value. The first compensation sensor is disposed on the physiological signal sensor. The signal processing device is coupled to the physiological signal sensor and the first compensation sensor. The signal processing device obtains through the first compensation sensor a failure region of the physiological signal sensor partially detached from the object to be detected and obtains a first failure compensation value according to the failure region, so as to compensate the physiological signal value sensed by the physiological signal sensor.

Abstract: A crossing frames encoding management method, a memory storage apparatus, and a memory control circuit unit are disclosed. The method includes: reading a tag swap information corresponding to a first physical group; encoding a first data; storing a first part of the encoded first data to at least one first physical unit corresponding to a first tag information in the first physical group; and storing a second part of the encoded first data to at least one second physical unit corresponding to a second tag information in the first physical group according to the tag swap information. The first tag information corresponds to a first crossing frames encoding group. The second tag information corresponds to a second crossing frames encoding group. The first crossing frames encoding group is different from the second crossing frames encoding group.

Abstract: A surface-treated copper foil including a treating surface, where the root mean square height (Sq) of the treating surface is in a range of 0.20 to 1.50 ?m and the texture aspect ratio (Str) of the treating surface is not greater than 0.65. When the surface-treated copper foil is heated at a temperature of 200° C. for 1 hour, the ratio of the integrated intensity of (111) peak to the sum of the integrated intensities of (111) peak, (200) peak, and (220) peak of the treating surface is at least 60%.

Abstract: A semiconductor device with different gate structures and a method of fabricating the same are disclosed. The a method includes forming a fin structure on a substrate, forming a thermal oxide layer on top and side surfaces of the fin structure, forming a polysilicon structure on the thermal oxide layer, doping portions of the fin structure uncovered by the polysilicon structure to form doped fin portions, forming a nitride layer on the polysilicon structure and the thermal oxide layer, forming an oxide layer on the nitride layer, doping the nitride layer with halogen ions, forming a source/drain region in the fin structure and adjacent to the polysilicon structure, and replacing the polysilicon structure with a gate structure.