Patents by Inventor Jung-A Yang

Jung-A Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11538763
    Abstract: A display device comprises a display panel substrate and a glass substrate over said display panel substrate, wherein said display panel substrate comprises multiple contact pads, a display area, a first boundary, a second boundary, a third boundary and a fourth boundary, wherein said display area comprises a first edge, a second edge, a third edge and a fourth edge, wherein said first boundary is parallel to said third boundary and said first and third edges, wherein said second boundary is parallel to said fourth boundary and said second and fourth edges, wherein a first least distance between said first boundary and said first edge, wherein a second least distance between said second boundary and said second edge, a third least distance between said third boundary and said third edge, a fourth distance between said fourth boundary and said fourth edge, and wherein said first, second, third and fourth least distances are smaller than 100 micrometers, and wherein said glass substrate comprising multiple meta
    Type: Grant
    Filed: July 11, 2021
    Date of Patent: December 27, 2022
    Inventor: Ping-Jung Yang
  • Patent number: 11532598
    Abstract: Provided is a semiconductor package structure including a first die having a first bonding structure thereon, a second die having a second bonding structure thereon, a metal circuit structure, and a first protective structure. The second die is bonded to the first die such that a first bonding dielectric layer of the first bonding structure contacts a second bonding dielectric layer of the second bonding structure. The metal circuit structure is disposed over a top surface of the second die. The first protective structure is disposed within the top surface of the second die, and sandwiched between the metal circuit structure and the second die.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Ming-Fa Chen
  • Publication number: 20220384326
    Abstract: A connector may include: a first substrate having a top surface, a bottom surface opposite to the top surface of the top substrate and a side surface joining an edge of the top surface of the first substrate and joining an edge of the bottom surface of the first substrate; a second substrate having a top surface, a bottom surface opposite to the top surface of the second substrate and a side surface joining an edge of the top surface of the second substrate and joining an edge of the bottom surface of the second substrate, wherein the side surface of the second substrate faces the side surface of the first substrate, wherein the top surfaces of the first and second substrates are coplanar with each other at a top of the connector and the bottom surfaces of the first and second substrates are coplanar with each other at a bottom of the connector; and a plurality of metal traces between, in a first horizontal direction, the side surfaces of the first and second substrates, wherein each of the plurality of metal
    Type: Application
    Filed: May 27, 2022
    Publication date: December 1, 2022
    Inventors: Ping-Jung Yang, Mou-Shiung Lin, Jin-Yuan Lee, Hsin-Jung Lo, Chiu-Ming Chou
  • Patent number: 11514259
    Abstract: A personal style database building apparatus and method in which communicate a plurality of clothing processing appliances, and a server with each other in a 5G communication environment by executing a loaded artificial intelligence (AI) algorithm and/or a machine learning algorithm. The personal style database building method according to an exemplary embodiment of the present disclosure includes analyzing first and second clothing image information collected from a first and a second clothing processing appliance to be built the first and the second clothing image information as first and second clothing record information in a database, comparing the first and the second clothing record information, and building merged record information in which the first and the second clothing record information in the database when a similarity between the first and the second clothing record information is equal to or higher than a predetermined reference value as a comparison result.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: November 29, 2022
    Assignee: LG ELECTRONICS INC.
    Inventors: In Jung Yang, Ja Hee Hur
  • Publication number: 20220359371
    Abstract: Methods and apparatus are disclosed for manufacturing metal contacts under ground-up contact pads within a device. A device may comprise a bottom metal layer with a bottom metal contact, a top metal layer with a top metal contact, and a plurality of middle metal layers. Any given metal layer of the plurality of middle metal layers comprises a metal contact, the metal contact is substantially vertically below the top metal contact, substantially vertically above the bottom metal contact, and substantially vertically above a metal contact in any metal layer that is below the given metal layer. The metal contacts may be of various and different shapes. All the metal contacts in the plurality of middle metal layers and the bottom metal contact may be smaller than the top metal contact, therefore occupying less area and saving more area for other functions such as device routing.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Chia-Wei Tu
  • Publication number: 20220336139
    Abstract: A coupled inductor has two coils made by film processes, wherein a first coil is disposed on a top surface of a magnetic sheet and a second coil is disposed on a bottom surface of the magnetic sheet, for controlling the variations of the gap between the two coils in a smaller range.
    Type: Application
    Filed: April 13, 2022
    Publication date: October 20, 2022
    Inventors: Li-Jung Yang, Xiang Jun Li, Chenlun Huang
  • Publication number: 20220336303
    Abstract: A method of forming a semiconductor package device includes: providing a substrate; bonding a first die to an upper surface of the substrate through a bonding layer; bonding a second die to the upper surface of the substrate through the bonding layer, the second die laterally separated from the first die; depositing an insulation material between the first die and the second die and filling a gap measured between sidewalk of the first die and the second die; forming a first interconnect layer over the first die and the second die to form the semiconductor package device; and performing a testing operation on semiconductor package device with the substrate in place. A Young's modulus of the substrate is greater than that of the insulation material.
    Type: Application
    Filed: July 5, 2022
    Publication date: October 20, 2022
    Inventors: HSIEN-WEI CHEN, CHING-JUNG YANG, MING-FA CHEN
  • Patent number: 11469200
    Abstract: A semiconductor device includes a substrate includes a first layer and a second layer over the first layer, a bump disposed over the second layer, a molding disposed over the second layer and surrounding the bump, and a retainer disposed over the second layer, wherein the retainer is disposed between the molding and a periphery of the substrate. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing several bumps on the substrate, disposing a retainer on the substrate and surrounding the bumps, and disposing a molding between the bumps and the retainer.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: October 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tung-Liang Shao, Yu-Chia Lai, Hsien-Ming Tu, Chang-Pin Huang, Ching-Jung Yang
  • Patent number: 11445912
    Abstract: The invention provides various methods for imaging a subject's cardiovascular system. The imaging method may be used to provide a diagnosis or prognosis of various cardiovascular diseases in the subject, without contrast agents or radioactive tracers, and further generating a Gaussian Mixture Model to obtain a reference value of a normal myocardium.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 20, 2022
    Assignee: Cedars-Sinai Medical Center
    Inventors: Rohan Dharmakumar, Hsin-Jung Yang
  • Patent number: 11445120
    Abstract: Disclosed are an information processing method and information processing apparatus which execute an installed artificial intelligence (AI) algorithm and/or machine learning algorithm to process a spoken utterance of a user in a 5G communication environment. The information processing method according to an embodiment of the present disclosure may include receiving a spoken utterance of a user and extracting, from the spoken utterance, a demonstrative pronoun referring to a target indicated by the user, determining an image capture region to be scanned by a camera according to the type of the demonstrative pronoun, recognizing the target indicated by the user from a result of scanning the image capture region, and feeding back a result of processing the spoken utterance to the user on the basis of a result of recognizing the target indicated by the user.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: September 13, 2022
    Assignee: LG ELECTRONICS INC.
    Inventors: In Jung Yang, Mi Seon Park, Ji-Won Kim
  • Publication number: 20220285279
    Abstract: A semiconductor structure includes a stacked die including a lower portion and an upper portion stacked upon the lower portion. The lower portion includes a first patterned conductive pad, a first conductive connector passing through the first patterned conductive pad, a first patterned dielectric layer covering the first patterned conductive pad and laterally isolating the first conductive connector from the first patterned conductive pad. The upper portion includes a second conductive connector bonded to the first conductive connector, and a second patterned dielectric layer bonded to the first patterned dielectric layer.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 8, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Jung Yang, Hsien-Wei Chen, Ming-Fa Chen
  • Publication number: 20220262765
    Abstract: Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region, a molding material around the integrated circuit die mounting region, and an interconnect structure over the molding material and the integrated circuit die mounting region. The interconnect structure has contact pads, and connectors are coupled to the contact pads. Two or more of the connectors have an alignment feature formed thereon.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 18, 2022
    Inventors: Ching-Jung Yang, Yen-Ping Wang
  • Publication number: 20220262772
    Abstract: A package structure includes first and second dies, an insulation structure, a through via, a dielectric layer and a redistribution layer. The second die electrically bonded to the first die includes a through substrate via. The insulation structure is disposed on the first die and laterally surrounds the second die. The through via penetrates through the insulation structure to electrically connect to the first die. The dielectric layer is disposed on the second die and the insulation structure. The redistribution layer is embedded in the dielectric layer and electrically connected to the through via. The redistribution layer includes a first barrier layer and a conductive layer on the first barrier layer. The through substrate via is electrically connected to the redistribution layer, and the conductive layer is in contact with a conductive post of the through via and separated from the through substrate via by the first barrier layer therebetween.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 18, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Ming-Fa Chen, Sung-Feng Yeh, Ying-Ju Chen
  • Patent number: 11417599
    Abstract: Methods and apparatus are disclosed for manufacturing metal contacts under ground-up contact pads within a device. A device may comprise a bottom metal layer with a bottom metal contact, a top metal layer with a top metal contact, and a plurality of middle metal layers. Any given metal layer of the plurality of middle metal layers comprises a metal contact, the metal contact is substantially vertically below the top metal contact, substantially vertically above the bottom metal contact, and substantially vertically above a metal contact in any metal layer that is below the given metal layer. The metal contacts may be of various and different shapes. All the metal contacts in the plurality of middle metal layers and the bottom metal contact may be smaller than the top metal contact, therefore occupying less area and saving more area for other functions such as device routing.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Chia-Wei Tu
  • Publication number: 20220238397
    Abstract: Provided is a semiconductor structure including an interconnect structure, disposed over a substrate; a pad structure, disposed over and electrically connected to the interconnect structure, wherein the pad structure comprises a metal pad and a dielectric cap on the metal pad, and the pad structure has a probe mark recessed from a top surface of the dielectric cap into a top surface of the metal pad; a protective layer, conformally covering the top surface of the dielectric cap and the probe mark; and a bonding structure, disposed over the protective layer, wherein the bonding structure comprises: a bonding dielectric layer at least comprising a first bonding dielectric material and a second bonding dielectric material on the first bonding dielectric material; and a first bonding metal layer disposed in the bonding dielectric layer and penetrating through the protective layer and the dielectric cap to contact the metal pad.
    Type: Application
    Filed: April 14, 2022
    Publication date: July 28, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Jie Chen
  • Publication number: 20220223621
    Abstract: Disclosed are three-dimensional semiconductor memory devices including an electrode structure including gate electrodes stacked in a first direction, a lower pattern group including lower vertical patterns that are in a lower portion of the electrode structure and are connected to the substrate, and an upper pattern group including upper vertical patterns that are in an upper portion of the electrode structure. The upper vertical patterns may be connected to the lower vertical patterns, respectively. The devices may also include two common source plugs spaced apart from each other in a second direction. The electrode structure may be between the two common source plugs. An upper portion of the lower pattern group has a first width in the second direction, an upper portion of the upper pattern group has a second width in the second direction, and the first width may be greater than the second width.
    Type: Application
    Filed: April 4, 2022
    Publication date: July 14, 2022
    Inventors: Taehee LEE, Hyunwook KIM, Eun-jung YANG
  • Publication number: 20220223494
    Abstract: A micro heat transfer component includes a bottom metal plate; a top metal plate; a plurality of sidewalls each having a top end joining the top metal plate and a bottom end joining the bottom metal plate, wherein the top and bottom metal plates and the sidewalls form a chamber in the micro heat transfer component; a plurality of metal posts in the chamber and between the top and bottom metal plates, wherein each of the metal posts has a top end joining the top metal plate and a bottom end joining the bottom metal plate; a metal layer in the chamber, between the top and bottom metal plates and intersecting each of the metal posts, wherein a plurality of openings are in the metal layer, wherein a first space in the chamber is between the metal layer and bottom metal plate and a second space in the chamber is between the metal layer and top metal plate; and a liquid in the first space in the chamber.
    Type: Application
    Filed: January 8, 2022
    Publication date: July 14, 2022
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin, Ping-Jung Yang
  • Publication number: 20220204375
    Abstract: Provided are a system and a method of treating wastewater. The system includes a forward osmosis (FO) liquid concentration apparatus and an electrodialysis (ED) apparatus. The FO liquid concentration apparatus increases the concentration of the salt in the wastewater to between 7% and 14%. The ED apparatus is disposed downstream of the FO liquid concentration apparatus and coupled to the FO liquid concentration apparatus to receive the wastewater introduced by the FO liquid concentration apparatus, and make the salt in the wastewater into an acid solution and a basic solution.
    Type: Application
    Filed: December 30, 2020
    Publication date: June 30, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Chia-Hua Ho, David Chiuni Wang, Tsui-Jung Yang, Sin-Yi Huang, Yi-Fong Pan, Po-I Liu, Guan-You Lin, Ren-Yang Horng, Teh-Ming Liang
  • Patent number: 11373953
    Abstract: A manufacturing method of a semiconductor structure includes at least the following steps. Forming a first portion includes forming a first patterned conductive pad with a first through hole on a first interconnect structure over a first semiconductor substrate; patterning a dielectric material over the first interconnect structure to form a first patterned dielectric layer with a first opening that passes through a portion of the dielectric material formed inside the first through hole to accessibly expose the first interconnect structure; and forming a conductive material inside the first opening and in contact with the first interconnect structure to form a first conductive connector laterally isolated from the first patterned conductive pad by the first patterned dielectric layer. A singulation process is performed to cut off the first patterned dielectric layer, the first interconnect structure, and the first semiconductor substrate to form a continuous sidewall of a semiconductor structure.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Jung Yang, Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 11367434
    Abstract: An electronic device, a method for obtaining an utterance intention of a user thereof, and a non-transitory computer-readable recording medium are provided. An electronic device according to an embodiment of the present disclosure may comprise: a microphone for receiving a user voice uttered by a user; and a processor for obtaining an utterance intention of a user on the basis of at least one word included in a user voice while the user voice is being input, providing response information corresponding to the obtained utterance intention, and updating the response information while providing the response information, on the basis of an additional word uttered after the at least one word is input.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: June 21, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-hyeon Lee, Hae-hun Yang, He-jung Yang, Jung-sup Lee, Hee-sik Jeon, Hyung-tak Choi