Patents by Inventor Jung-An Wang

Jung-An Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942145
    Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chuan Yang, Jui-Wen Chang, Feng-Ming Chang, Kian-Long Lim, Kuo-Hsiu Hsu, Lien Jung Hung, Ping-Wei Wang
  • Patent number: 11940388
    Abstract: Example methods are provided to improve placement of an adaptor (210,220) to a mobile computing device (100) to measure a test strip (221) coupled to the adaptor (220) with a camera (104) and a screen (108) on a face of the mobile computing device (100). The method may include displaying a light area on a first portion of the screen (108). The first portion may be adjacent to the camera (104). The light area and the camera (104) may be aligned with a key area of the test strip (221) so that the camera (104) is configured to capture an image of the key area. The method may further include providing first guiding information for a user to place the adaptor (210,220) to the mobile computing device (100) according to a position of the light area on the screen (108).
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: March 26, 2024
    Assignee: IXENSOR CO., LTD.
    Inventors: Yenyu Chen, An Cheng Chang, Tai I Chen, Su Tung Yang, Chih Jung Hsu, Chun Cheng Lin, Min Han Wang, Shih Hao Chiu
  • Patent number: 11944017
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes an insulation layer. A bottom electrode via is disposed in the insulation layer. The bottom electrode via includes a conductive portion and a capping layer over the conductive portion. A barrier layer surrounds the bottom electrode via. A magnetic tunneling junction (MTJ) is disposed over the bottom electrode via.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tai-Yen Peng, Yu-Shu Chen, Chien Chung Huang, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
  • Publication number: 20240097888
    Abstract: In a file sharing system, a key manager unit realizes a correspondence between the first user identifier and the first public key in response to a registration request of the first user, generates a first key material for encrypting the first file into a first encrypted file, and generates a first credential according to the first user identifier, the first file identifier, the first public key and the first key material after receiving an access-right claim request to the first file from the first user. A file storage unit stores the first encrypted file and the first credential. The first user uses the first user identifier, the first file identifier and the first private key to retrieve the first key material out of the first credential, and uses the first key material to decrypt the first encrypted file into the first file.
    Type: Application
    Filed: September 18, 2023
    Publication date: March 21, 2024
    Inventors: CHIA-JUNG LIANG, CHIHHUNG LIN, CHIH-PING HSIAO, YU-JIE SU, CHIA-HSIN CHENG, TUN-HOU WANG, MENG-CHAO TSAI, YUEH-CHIN LIN
  • Publication number: 20240099150
    Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
  • Patent number: 11935795
    Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hung Wang, Tsung-Lin Lee, Wen-Chih Chiang, Kuan-Jung Chen
  • Publication number: 20240087960
    Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 14, 2024
    Inventors: Yu-Lien HUANG, Ching-Feng FU, Huan-Just LIN, Fu-Sheng LI, Tsai-Jung HO, Bor Chiuan HSIEH, Guan-Xuan CHEN, Guan-Ren WANG
  • Publication number: 20240089950
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a first user equipment (UE) may transmit, to a second UE, an indication of at least one sidelink unified transmission configuration indicator (TCI) state, wherein the at least one sidelink unified TCI state includes at least one of: a joint forward link and reverse link TCI state, a separate forward link TCI state, or a separate reverse link TCI state. The first UE may communicate with the second UE on at least one of the forward link or the reverse link based at least in part on the indication of the sidelink unified TCI state. Numerous other aspects are described.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 14, 2024
    Inventors: Hua WANG, Sony AKKARAKARAN, Yan ZHOU, Tianyang BAI, Jung Ho RYU, Jing SUN, Tao LUO, Junyi LI
  • Publication number: 20240088986
    Abstract: Methods, systems, and devices for wireless communications are described. A receiving user equipment (UE) may broadcast messages containing inter-UE cooperation (IUC) information using multiple beams. The IUC information transmitted on each beam may be different for each beam of the receiving UE. For example, each IUC information may contain different preferred resources or non-preferred resources for the receiving UE to receive a transmission from a transmitting UE. The transmitting UE may receive a message containing IUC information from one of the beams of the receiving UE and transmit a signal using resources based on the IUC information contained in the received message. In some examples, the transmitting UE may transmit a channel busy ratio (CBR) request to a receiving UE. The CBR request may specify a transmission configuration indicator (TCI) state, spatial relation, spatial domain filter, or beam according to which the receiving UE is to measure the CBR.
    Type: Application
    Filed: September 12, 2022
    Publication date: March 14, 2024
    Inventors: Jung Ho Ryu, Sony Akkarakaran, Hua Wang, Gabi Sarkis, Tao Luo, Junyi Li, Wooseok Nam
  • Publication number: 20240089746
    Abstract: Methods, systems, and devices for wireless communications that support inter-user equipment (UE) coordination (IUC) for beamformed communications are described. A first UE may receive, using a first spatial filter, a first sidelink control message including a first sidelink resource reservation associated with a second UE. Additionally, or alternatively, the first UE may receive, using a second spatial filter, a second sidelink control message including a second sidelink resource reservation associated with a third UE. The first UE may transmit, to the second UE or the third UE, an IUC message that indicates a conflict between the first sidelink resource reservation and the second sidelink resource reservation. The IUC message that indicates a conflict may be based on a relationship between the first spatial filter used to receive the first sidelink resource reservation and the second spatial filter used to receive the second sidelink resource reservation.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 14, 2024
    Inventors: Jung Ho Ryu, Sony Akkarakaran, Gabi Sarkis, Hua Wang, Junyi Li, Tao Luo
  • Publication number: 20240079392
    Abstract: A semiconductor structure includes a first tier, a redistribution circuit structure, and a second tier. The first tier includes at least one first die. The redistribution circuit structure is disposed on the first tier and electrically coupled to the at least one first die, where the redistribution circuit structure has a multi-layer structure and includes a vertical connection structure continuously extending from a first side of the redistribution circuit structure to a second side of the redistribution circuit structure, and the first side is opposite to the second side along a stacking direction of the first tier and the redistribution circuit structure. The second tier includes a plurality of second dies, and is disposed on and electrically coupled to the redistribution circuit structure.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang WANG, Tso-Jung Chang, Jeng-Shien Hsieh, Shih-Ping Lin, Chih-Peng Lin, Chieh-Yen Chen, Chen-Hua Yu
  • Publication number: 20240079758
    Abstract: An electronic device includes a metal back cover, a metal frame, and a first, second, third, and fourth radiators. The metal frame includes a discrete part and two connection parts. The connection parts are located by two sides of the discrete part, separated from the discrete part, and connected to the metal back cover. A U-shaped slot is formed between the discrete part and the metal back cover and between the discrete part and the connection parts. The first radiator is separated from the discrete part and includes a feed end. The second, third, and fourth radiators are connected to the discrete part and the metal back cover. The third radiator is located between the first and second radiators. The first radiator is located between the third and fourth radiators. The discrete part and the first, second, third, and fourth radiators form an antenna module together.
    Type: Application
    Filed: August 2, 2023
    Publication date: March 7, 2024
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Chao-Hsu Wu, Chih-Wei Liao, Hau Yuen Tan, Shih-Keng Huang, Wen-Hgin Chuang, Lin-Hsu Chiang, Chang-Hua Wu, Han-Wei Wang, Chun-Jung Hu
  • Patent number: 11921552
    Abstract: A computer chassis includes walls defining an airspace containing heat-generating components (e.g., storage drives). The airspace is divided into first and second regions, such as by a printed circuit board supporting the heat-generating components within the first region. An air input feeds both the first region and second region. Input air going through the first region first passes by a forward set of heat-generating components before continuing to a rearward set of heat-generating components to extract heat therefrom. Input air going through the second region bypasses the forward set of heat-generating components before being directed out through an air opening partway down the length of the chassis, after which this air passes by a rearward set of heat-generating components to extract heat.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: March 5, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chao-Jung Chen, Yu-Nien Huang, Jen-Hui Wang
  • Publication number: 20240071758
    Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a gate electrode layer on the p-type semiconductor layer, and patterning the gate electrode layer to form a gate electrode. Preferably, the gate electrode includes an inclined sidewall.
    Type: Application
    Filed: September 23, 2022
    Publication date: February 29, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Tung Yeh, You-Jia Chang, Bo-Yu Chen, Yun-Chun Wang, Ruey-Chyr Lee, Wen-Jung Liao
  • Publication number: 20240073900
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a transmitter user equipment (UE) may identify a plurality of beams that are configured for transmitting one or more sidelink communications via one or more sidelink resources. The UE may transmit sidelink control information that indicates to reserve the one or more sidelink resources and that includes an explicit beam indication or a beam hopping indication associated with the plurality of beams. Numerous other aspects are described.
    Type: Application
    Filed: August 25, 2022
    Publication date: February 29, 2024
    Inventors: Hua WANG, Sony AKKARAKARAN, Tianyang BAI, Yan ZHOU, Jung Ho RYU, Tao LUO, Junyi LI
  • Publication number: 20240073865
    Abstract: Method and apparatus for enhanced inter-UE coordination. The apparatus transmits, to a second UE, an IUC request for an IUC message indicating preferred resources or non-preferred resources for transmission of a signal by a third UE. The apparatus receives, from the second UE, the IUC message indicating the preferred resources or the non-preferred resources for the transmission of the signal by the third UE. The apparatus may select transmission resources for the third UE based at least on the IUC message from the second UE indicating the preferred resources or the non-preferred resources for transmission by the third UE.
    Type: Application
    Filed: August 16, 2022
    Publication date: February 29, 2024
    Inventors: Jung Ho RYU, Sony AKKARAKARAN, Junyi LI, Jelena DAMNJANOVIC, Hua WANG, Tao LUO
  • Publication number: 20240066767
    Abstract: A method of manufacturing a multicolor-foamed shoe body by supercritical foaming includes step S1 to step S3: step S1: provide a plurality of cold shot model molds and inject a plurality of foaming materials in different colors into a cavity of each of the cold shot model molds to form a plurality of cold shot models in different colors that is unfoamed; step S2: place the cold shot models in a hot-pressing mold for hot pressing to make a contacting surface of any two of the cold shot models that are adjacent engage with each other due to heating to foam a semi-finished product; and step S3: place the semi-finished product in a supercritical foaming autoclave for foam molding to obtain the multicolor-foamed shoe body. Additionally, the multicolor-foamed shoe body manufactured by the method is also disclosed in the present invention.
    Type: Application
    Filed: March 9, 2023
    Publication date: February 29, 2024
    Inventors: PAO-HSIN WANG, YI-JUNG HUANG
  • Publication number: 20240071413
    Abstract: The present disclosure generally relates to a dual free layer (DFL) read head and methods of forming thereof. In one embodiment, a method of forming a DFL read head comprises depositing a DFL sensor, defining a stripe height of the DFL sensor, depositing a rear bias (RB) adjacent to the DFL sensor, defining a track width of the DFL sensor and the RB, and depositing synthetic antiferromagnetic (SAF) soft bias (SB) side shields adjacent to the DFL sensor. In another embodiment, a method of forming a DFL read head comprises depositing a DFL sensor, defining a track width of the DFL sensor, depositing SAF SB side shields adjacent to the DFL sensor, defining a stripe height of the DFL sensor and the SAF SB side shield, depositing a RB adjacent to the DFL sensor and the SAF SB side shield, and defining a track width of the RB.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ming MAO, Yung-Hung WANG, Chih-Ching HU, Chen-Jung CHIEN, Carlos CORONA, Hongping YUAN, Ming JIANG, Goncalo Marcos BAIÃO DE ALBUQUERQUE
  • Patent number: 11915971
    Abstract: A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Wang-Jung Hsueh, Kuo-Yi Chao, Mei-Yun Wang
  • Patent number: 11913876
    Abstract: An optical water-quality detection apparatus includes a detection device, a biofilm-inhibition light source, a detection light source and a sensor. The detection device includes a detection chamber. The biofilm-inhibition light source is disposed outside the detection chamber and configured to emit biofilm-inhibition light. The detection light source is disposed outside the detection chamber and configured to emit detection light. The sensor is configured to sense the detection light penetrating the detection chamber. A beam of the detection light and a beam of the inhibition light overlaps as penetrating the detection chamber.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: February 27, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chia-Jung Chang, Jui-Hung Tsai, Ying-Hao Wang, Chih-Hao Hsu