Abstract: A battery charging apparatus includes a battery compartment having a receptacle that is configured to receive a battery pack. The battery charging apparatus includes a first heat exchange module and/or a second heat exchange module. The first heat exchange module includes a plenum surrounding the receptacle, where the plenum includes a chamber to receive a fluid. The plenum also includes a plurality of flow guides disposed in the chamber to define a variable flow passage for the fluid. The second heat exchange module includes a battery connector and a heat sink thermally coupled to the battery connector. The heat sink is arranged to dissipate thermal energy from the battery pack.

Abstract: Embodiments of the instant disclosure relate to novel methods for treatment of one or more pathologic entities of Type 2 diabetes. In certain embodiments, methods concern reducing the risk of developing, preventing and/or treating a pathologic entity of Type 2 diabetes or other condition having a pathologic entity component by administering to a subject in need thereof a granulocyte macrophage colony stimulating factor (GM-CSF) or recombinantly produced molecule or fragment thereof, or an analog thereof. In other embodiments, methods concern decreasing pancreatic islet amyloid deposition in a subject by administering to the subject, GM-CSF or recombinantly produced molecule or fragment thereof, or an analog thereof, wherein the subject has pancreatic islet amyloid deposition.

Abstract: A display is provided. The display device includes a display area and a non-display area located around the display area; a base layer; an organic light-emitting diode (OLED) that is located on the base layer in the display area; and a first crack detection line that is located on the base layer in the non-display area; wherein the first crack detection line comprises a first line that extends substantially in a first direction along a first edge of the display area, a second line that is separated from the first line and extends substantially in the first direction, and a third line that is connected to an end of the first line and an end of the second line, wherein a cross-sectional shape of the first line in a second direction crossing the first direction is inversely tapered.

Abstract: A pixel array is provided. The pixel array includes a plurality of pixels, wherein each of the pixels includes a light emitting diode, a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor receives a first data signal and a first scan signal. The second transistor is coupled to the first transistor and an anode of the light emitting diode. The third transistor receives a system high voltage and a first control signal, and is coupled to the second transistor. The fourth transistor is coupled to an anode of a light emitting diode of an adjacent pixel, a control terminal of the third transistor, and a cathode of the light emitting diode. The fifth transistor is coupled to the cathode of the light emitting diode, and receives a second control signal and a system low voltage.

Abstract: In a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. Overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. The overlay offset data is determined based on the received thickness variation data. The overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. A location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. The second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.

Abstract: An integrated circuit includes a metallization pattern having first and second conductive features, an etch stop layer over the metallization pattern, a memory device, a bottom electrode via, a third conductive feature, and a dielectric feature. The etch stop layer has first and second portions over the first and second conductive features, respectively. The bottom electrode via is in the first portion of the etch stop layer and electrically connecting the memory device over the first portion of the etch stop layer to the first conductive feature. The third conductive feature is in the second portion of the etch stop layer and electrically connected to the second conductive feature. The dielectric feature is between the first and second portions of the etch stop layer and in contact with sidewalls of the first and second portions of the etch stop layer.

Abstract: Methods and systems for dry etching are disclosed. The methods and systems use a showerhead with a perforated plate. The perforated plate includes a primary solid zone having no holes; a first annular zone comprising a first plurality of holes with a first total hole area; a secondary solid zone having no holes; a second annular zone comprising a second plurality of holes with a second total hole area; a third annular zone comprising a third plurality of holes with a third total hole area; and a fourth annular zone comprising a fourth plurality of holes with a fourth total hole area. The third total hole area is greater than the first total hole area and less than the second total hole area, and the fourth total hole area is greater than the second total hole area. Dry etched wafers using these systems have improved edge uniformity and improved yield.

Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.

Abstract: A semiconductor structure with an air gap includes a dielectric stack having a first dielectric layer on a substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer. A first conductive layer and a second conductive layer are disposed in the dielectric stack. The first conductive layer and the second conductive layer are coplanar. A cross-like-shaped air gap is disposed in the dielectric stack between the first and second conductive layers. An oxide layer is disposed on a sidewall of the second dielectric layer within the cross-like-shaped air gap.

Abstract: An in-plane magnetized spin-orbit magnetic device is provided. The in-plane magnetized spin-orbit magnetic device includes a heavy metal layer, an upper electrode and a magnetic tunnel junction. The magnetic tunnel junction is disposed between the heavy metal layer and the upper electrode. The magnetic tunnel junction includes a free layer and a pinned layer. The free layer is disposed on the heavy metal layer, and the free layer has a first film plane area. The pinned layer is disposed on the free layer, and the pinned layer has a second film plane area. There is a preset angle between a long axis direction of a film plane shape of the free layer and a long axis direction of a film plane shape of the pinned layer, and the first film plane area is larger than the second film plane area.

Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.

Abstract: A method for fabricating magnetic tunnel junction (MTJ) pillars is provided. The method includes following operations. A MTJ stack of layers including a first magnetic layer, a tunnel barrier layer overlying the first magnetic layer, and a second magnetic layer overlying the tunnel barrier layer is provided. A first patterning step is carried out by using a reactive ion etching. In the first patterning step, the second magnetic layer and the tunnel barrier layer are etched to form one or more pillar structures and a protection layer is formed and covers sidewalls of the pillar structures.

Abstract: A seismic isolation device comprises an isolation support and an inerter unit arranged on the side of the isolation support, the isolation support having an upper plate and a lower plate, the inerter unit having a rotating rod extending to the side of the lower plate and a flywheel linked with the rotating rod, wherein when the upper and lower plates of the present invention undergo relative displacement due to the occurrence of an earthquake, the inerter unit provide an inertance to reduce the displacement reaction, thereby providing better seismic isolation effect.

Abstract: The disclosure provides an electronic apparatus. The electronic apparatus includes a substrate, a first metal layer, an insulating layer, a first conductor, an electronic assembly and a transistor circuit die. The first metal layer is disposed on the substrate. The insulating layer is disposed on the substrate. The first conductor is formed in a first via of the insulating layer. The electronic assembly is disposed on the substrate and electrically connected to the first metal layer through the first conductor. The transistor circuit die is electrically connected to the first metal layer.

Abstract: A guiding system and a guiding method for ultrasound scanning operation are provided. The guiding system includes a handheld guiding device, a display device, an ultrasound scanning device, a prompting device, and a control host. When the handheld guiding device generates a first physical motion, the control host detects the first physical motion and generates navigation prompting information accordingly. The prompting device is suitable for presenting the navigation prompting information to guide the ultrasound scanning device to move to generate a second physical motion. The control host captures an ultrasound image via the ultrasound scanning device and sends the ultrasound image to the display device at a guiding end for display.

Abstract: A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL.

Abstract: An integrated circuit includes a dielectric layer, a memory device, and a resistor. The memory device includes a bottom electrode via, a bottom electrode, a resistance switching element, and a top electrode. The bottom electrode via is in the dielectric layer. The dielectric layer has a first portion extending along sidewalls of the bottom electrode via, a second portion extending laterally from the first portion, and a third portion. The bottom electrode is over the bottom electrode via. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element. The resistor is over the third portion of the dielectric layer. A thickness of the third portion of the dielectric layer is greater than a thickness of the second portion of the dielectric layer.

Abstract: A method for fabricating magnetic tunnel junction (MTJ) pillars is provided. The method includes following operations. A MTJ stack of layers including a first magnetic layer, a tunnel barrier layer overlying the first magnetic layer, and a second magnetic layer overlying the tunnel barrier layer is provided. A first patterning step is carried out by using a reactive ion etching. In the first patterning step, the second magnetic layer and the tunnel barrier layer are etched to form one or more pillar structures and a protection layer is formed and covers sidewalk of the pillar structures.

Abstract: A magnetic memory structure includes a heavy-metal layer, a plurality of magnetic tunneling junction (MTJ) layer, a conductive layer and an insulation layer. In an example, the pinned-layer of the MTJ layers are arranged in a string form and disposed over the barrier-layer. In an example also disclosed, the pinned-layer, the free-layer of the MTJ layers are arranged in a string form. Whereas the pinned-layers are disposed over the barrier-layer and the free-layers are disposed over the heavy-metal layer. The conductive layer is formed under the heavy-metal layer and includes a first conductive portion and a second conductive portion separated from each other and connected with two end of the heavy-metal layer respectively. The insulation layer fills up an interval between the first conductive portion and the second conductive portion. The conductive layer has an electric conductivity higher than that of the heavy-metal layer.

Abstract: In a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. Overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. The overlay offset data is determined based on the received thickness variation data. The overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. A location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. The second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.