Abstract: The present invention produces a ferrite magnetic material having a remarkably higher maximum energy product ((BH)max) than a conventional ferrite magnetic material through the induction of a high saturation magnetization and a high anisotropic magnetic field by simultaneously adding Co and Zn to substitute some of Fe and adjusting the content ratio of Zn/Co. In addition, the present invention can produce a desired magnetic material at a lower cost than a conventional CaLaCo-based ferrite magnetic material substituted with only Co by using Zn, which is relatively at least seven times cheaper than Co, together with Co.

Abstract: An integrated semiconductor device includes a first transistor and a second transistor formed on a semiconductor substrate, and an isolation structure located adjacent to the transistors, including deep trenches, trapping regions formed between the deep trenches, and trench bottom doping regions formed at the end of each of the deep trenches, wherein each of the trapping regions includes a buried layer, a well region formed on the buried layer, and a highly doped region formed on the well region.

Abstract: Provided is an ink composition for an inkjet print steel plate, an inkjet print steel plate using the same, and a method for producing an inkjet print steel plate. The ink composition comprises: a linear acrylate-based oligomer; a reactive acrylate-based monomer; an ultraviolet curable initiator; at least one selected from the group consisting of a dye and a pigment; and at least one selected from the group consisting of an antioxidant, an antifoaming agent, and a dispersant.

Abstract: A memory device and a method of operating the same. The memory device may include a memory block including a plurality of pages, and a control logic configured to include at least one register in which a plurality of program algorithms and a plurality of pieces of operation information are stored, select any one of the program algorithms in response to an address of a program target page, among the pages, and perform a program operation on the program target page based on the selected program algorithm and operation information corresponding to the selected program algorithm.

Abstract: A memory device may include a gate structure including a plurality of gate electrode layers and a plurality of insulating layers alternately stacked on a substrate, a plurality of etching stop layers, extending from the insulating layers respectively, being on respective lower portions of the gate electrode layers; and a plurality of contacts connected to the gate electrode layers above upper portions of the etching stop layers, respectively, wherein respective ones of the etching stop layers include an air gap therein.

Abstract: Disclosed is a method for preparing a hot-melt adhesive composition and a hot-melt adhesive composition prepared thereby. The method comprises: preparing and mixing raw materials, including a butyl rubber, an ethylene propylene diene (EPDM) rubber, a styrene block copolymer, an amorphous poly-alpha-olefin (APAO) and a tackifier resin; and performing vacuum degassing of the mixed raw materials, wherein the styrene block copolymer comprises a styrene-isoprene-styrene (SIS) rubber. The hot-melt adhesive composition has high resistance in temperature cycles between low and high temperatures so as to maintain its physical properties, and thus has an excellent property of sealing a headlamp for a long period of time until the end of the lifespan of the headlamp. Also, the composition generates no gas in the sealed state of the headlamp, and thus does not create bubbles or voids and does not pose a water tightness problem.

Abstract: A semiconductor memory device may include a memory cell array. The semiconductor memory device may include a peripheral circuit coupled to the memory cell array through word lines. The semiconductor memory device may include an overdrive setting unit configured for determining an overdrive set parameter of an overdrive operation using an operation voltage applied to the word lines.

Abstract: A method for receiving a streaming service is disclosed. The method for receiving a streaming service may be a method performed at a terminal for receiving a streaming service for a video content coded in a layered manner and may include the steps of: (a) sequentially requesting a transmission of at least one video data for a basic layer to be stored in the idle space of a buffer; and (b) sequentially requesting a transmission of video data for a layer of an increased level if the buffer does not have idle space, performed during the decoding of video data corresponding to a single video chunk, where step (b) may be repeated with the level of the layer increased during the decoding of video corresponding to a single video chunk.

Abstract: A semiconductor memory apparatus includes a driving voltage providing circuit suitable for selectively providing a first driving voltage, a second driving voltage, a third driving voltage, a ground voltage, and a precharge voltage to a first driving line and a second driving line in response to an active signal, a cell characteristic information signal, and a precharge signal. The semiconductor memory apparatus also includes a sense amplifier suitable for operating by being applied with voltages provided from the first and second driving lines.

Abstract: A semiconductor device and or method of operating the same may be provided. The semiconductor device may include a pass circuit unit configured to connect global signal lines to signal lines to set voltage levels of the signal lines.

Abstract: An integrated semiconductor device includes a first transistor and a second transistor formed on a semiconductor substrate, and an isolation structure located adjacent to the transistors, including deep trenches, trapping regions formed between the deep trenches, and trench bottom doping regions formed at the end of each of the deep trenches, wherein each of the trapping regions includes a buried layer, a well region formed on the buried layer, and a highly doped region formed on the well region.

Abstract: A semiconductor device may include a repair address storage circuit, an address comparison circuit, and a word line selection circuit. The repair address storage circuit may store a first repair address and a second repair address. The address comparison circuit may generate a first comparison signal by comparing an input address and the first repair address, and may generate a second comparison signal by comparing the input address and the second repair address. The word line selection circuit may generate a first redundancy word line select signal corresponding to the first comparison signal and a second redundancy word line select signal corresponding to the second comparison signal, based on the first comparison signal and the second comparison signal.

Abstract: A semiconductor device may include a repair address storage circuit, an address comparison circuit, and a word line selection circuit. The repair address storage circuit may store a first repair address and a second repair address. The address comparison circuit may generate a first comparison signal by comparing an input address and the first repair address, and may generate a second comparison signal by comparing the input address and the second repair address. The word line selection circuit may generate a first redundancy word line select signal corresponding to the first comparison signal and a second redundancy word line select signal corresponding to the second comparison signal, based on the first comparison signal and the second comparison signal.

Abstract: Semiconductor devices are provided. A semiconductor device includes a stack of alternating insulation layers and gate electrodes. The semiconductor device includes a channel material in a channel recess in the stack. The semiconductor device includes a charge storage structure on the channel material, in the channel recess. Moreover, the semiconductor device includes a gate insulation layer on the channel material. The gate insulation layer undercuts a portion of the channel material. Related methods of forming semiconductor devices are also provided.

Abstract: Provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory cell array including a plurality of memory blocks, each including dummy cells coupled to dummy word lines and normal memory cells coupled to normal word lines, and a peripheral circuit configured to perform an erase operation on a memory block selected from among the plurality of memory blocks. The semiconductor memory device may include control logic configured to control the peripheral circuit so that a pre-program voltage pulse is applied both to the dummy word lines and to the normal word lines, and dummy word line voltages to be applied to the dummy word lines may be respectively controlled while an erase voltage is applied to a common source line of the selected memory block.

Abstract: In an embodiment, a semiconductor memory device may include a memory cell array, a plurality of page buffers, and a control logic. The memory cell array may include a plurality of memory cells. The plurality of page buffers may be coupled to a plurality of bit lines of the memory cell array, respectively. The control logic may control the plurality of page buffers to perform a read operation on the memory cell array. Each of the plurality of page buffers may perform data sensing by changing a voltage of a page buffer sensing signal after an internal node is precharged.

Abstract: Provided herein is a semiconductor memory device and a method for operating the same. The semiconductor memory device may include a memory cell array including a plurality of memory blocks, each including dummy cells coupled to dummy word lines and normal memory cells coupled to normal word lines, a peripheral circuit configured to perform an erase operation on a memory block selected from among the plurality of memory blocks and control logic configured to control the peripheral circuit, during the erase operation, to apply a pre-program voltage pulse to the dummy word lines and the normal word lines, and to control application of dummy word line voltages to the dummy word lines based on Erase-Write (EW) cycling information while applying an erase voltage to a common source line of the selected memory block, wherein the EW cycling information indicates a number of erase-write cycles of the selected memory block.

Abstract: Provided herein may be a control logic, semiconductor memory device, method of operating the control logic, and or method of operating the semiconductor memory device. The semiconductor memory device may include a control logic. The control logic may be configured to control a program voltage to be applied to the selected word line. The control logic may be configured to control a pass voltage to be applied to an unselected word line.

Abstract: A gas injection apparatus injecting process gases toward a substrate includes a base part, a first gas injection part on the base part, the first gas injection part to inject a first gas including a reaction-inhibiting functional group, a second gas injection part spaced apart from the first gas injection part in one direction on the base part, the second gas injection part to inject a second gas including a precursor of a specific material, and a third gas injection part spaced apart from the second gas injection part in the one direction on the base part, the third gas injection part to inject a third gas reacting with the precursor of the specific material.

Abstract: Provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory cell array including a plurality of memory blocks, each including dummy cells coupled to dummy word lines and normal memory cells coupled to normal word lines, and a peripheral circuit configured to perform an erase operation on a memory block selected from among the plurality of memory blocks. The semiconductor memory device may include control logic configured to control the peripheral circuit so that a pre-program voltage pulse is applied both to the dummy word lines and to the normal word lines, and dummy word line voltages to be applied to the dummy word lines may be respectively controlled while an erase voltage is applied to a common source line of the selected memory block.