Abstract: A semiconductor device includes a semiconducting metal oxide fin located over a lower-level dielectric material layer, a gate dielectric layer located on a top surface and sidewalls of the semiconducting metal oxide fin, a gate electrode located on the gate dielectric layer and straddling the semiconducting metal oxide fin, an access-level dielectric material layer embedding the gate electrode and the semiconducting metal oxide fin, a memory cell embedded in a memory-level dielectric material layer and including a first electrode, a memory element, and a second electrode, and a bit line overlying the memory cell. The first electrode may be electrically connected to a drain region within the semiconducting metal oxide fin through a first electrically conductive path, and the second electrode is electrically connected to the bit line.

Abstract: An organic electroluminescent device including a first electrode, a second electrode, and an organic layer formed between the first electrode and the second electrode. The organic layer includes a light emitting layer formed using a solution containing an organic electroluminescent material and a solvent. The organic electroluminescent material includes a host and a dopant, and the host is one or more compounds represented by [Formula A] below.

Abstract: A semiconductor package includes a package substrate, an interposer disposed on the package substrate, and a first semiconductor chip disposed on the interposer. The interposer includes a first semiconductor substrate and a first dielectric layer disposed on the first semiconductor substrate. The first dielectric layer includes a first scribe lane region. The first scribe lane region is below the first semiconductor chip along a first direction that is perpendicular to a top surface of the first semiconductor substrate. The first scribe lane region is spaced apart from a lateral surface of the interposer.

Abstract: An organic electroluminescent device including a first electrode, a second electrode, and an organic layer formed between the first electrode and the second electrode. The organic layer includes a light emitting layer formed using a solution containing an organic electroluminescent material and a solvent. The organic electroluminescent material includes a host and a dopant, and the host is one or more compounds represented by [Formula A] below.

Abstract: An organic electroluminescent device including a first electrode, a second electrode, and an organic layer formed between the first electrode and the second electrode. The organic layer includes a light emitting layer formed using a solution containing an organic electroluminescent material and a solvent. The organic electroluminescent material includes a host and a dopant, and the host is one or more compounds represented by [Formula A] below.

Abstract: A thin film transistor includes an active layer located over a substrate, a first gate stack including a stack of a first gate dielectric and a first gate electrode and located on a first surface of the active layer, a pair of first contact electrodes contacting peripheral portions of the first surface of the active layer and laterally spaced from each other along a first horizontal direction by the first gate electrode, a second contact electrode contacting a second surface of the active layer that is vertically spaced from the first surface of the active layer, and a pair of second gate stacks including a respective stack of a second gate dielectric and a second gate electrode and located on a respective peripheral portion of a second surface of the active layer.

Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices which meet reduced thickness, lower thermal budget, and Vt requirements, and have improved device performance and reliability. Advantageously, the embodiments of the present disclosure provide methods of manufacturing electronic devices that achieve desired dipole effect without an annealing process. To achieve desired dipole effect that is “thinner” than 3 ?, embodiments of the disclosure advantageously include methods of controlling surface adsorption equilibrium and, in turn, controlling the fraction of substrate surface atomic sites that are occupied by dipole species, which is not considered to be achievable by ALD processes.

Abstract: A transistor structure including a substrate, a gate structure, first pocket doped regions, second pocket doped regions, and source/drain extension regions, and source/drain regions is provided. The gate structure is located on the substrate. The first pocket doped regions are located in the substrate aside the gate structure. A dopant of the first pocket doped region includes a group IVA element. The second pocket doped regions are located in the substrate aside the gate structure. A depth of the second pocket doped region is greater than a depth of the first pocket doped region. The source/drain extension regions are located in the first pocket doped regions. The source/drain regions are located in the substrate aside the gate structure. The source/drain extension region is located between the source/drain region and the gate structure.

Abstract: A method for inhibiting the metastasis of triple-negative breast cancer, which includes administering to a subject in need thereof a pharmaceutical composition containing rosoxacin or a pharmaceutically acceptable salt thereof.

Abstract: Disclosed herein is a method for alleviating a chronic liver disease, comprising administrating to a subject in need thereof a pharmaceutical composition containing rosoxacin.

Abstract: A memory device including bit lines, auxiliary lines, selectors, and memory cells is provided. The word lines are intersected with the bit lines. The auxiliary lines are disposed between the word lines and the of bit lines. The selectors are inserted between the bit lines and the auxiliary lines. The memory cells are inserted between the word lines and the auxiliary lines.

Abstract: A polymeric hollow fiber membrane is provided having a crosslinked selective layer formed by sequentially performing coating of a polymer precursor on a crosslinked polymeric hollow fiber membrane support and thermal condensation and thermal crosslinking thereof, a carbon molecular sieve hollow fiber membrane, methods for producing the same, and methods of separating gases using the same. The polymeric hollow fiber membrane and the carbon molecular sieve hollow fiber membrane each have a thin crosslinked selective layer and excellent plasticization resistance and separation performance. Accordingly, the polymeric hollow fiber membrane and the carbon molecular sieve hollow fiber membrane, each of which has a thin crosslinked selective layer, can be effectively used in the separation of a mixed gas.

Abstract: A thin film transistor includes an active layer located over a substrate, a first gate stack including a stack of a first gate dielectric and a first gate electrode and located on a first surface of the active layer, a pair of first contact electrodes contacting peripheral portions of the first surface of the active layer and laterally spaced from each other along a first horizontal direction by the first gate electrode, a second contact electrode contacting a second surface of the active layer that is vertically spaced from the first surface of the active layer, and a pair of second gate stacks including a respective stack of a second gate dielectric and a second gate electrode and located on a respective peripheral portion of a second surface of the active layer.

Abstract: A semiconductor package comprising a package substrate that extends in a first direction and a second direction perpendicular to the first direction, a plurality of logic dies and a memory stack structure on the package substrate, and an interposer substrate mounted in the package substrate. The memory stack structure vertically overlaps the interposer substrate. Each of the logic dies includes a first part that is horizontally offset from the interposer substrate and a second part that vertically overlaps the interposer substrate. The interposer substrate includes an interlayer dielectric layer and a plurality of wiring lines in the interlayer dielectric layer. The memory stack structure is electrically connected to at least one of the logic dies through the wiring lines of the interposer substrate.

Abstract: The present invention provides a practical protection performance test evaluation technology of CBRN protective clothing according to mass transfer characteristics of an aerosol, which is to break away from the existing static CBRN protection test cell and reflect an air flow around the CBRN protection and body motions of individual soldiers, and dynamically design a Swatch test cell in a geometric shape that can be installed inside a wind tunnel, and reflect an aerosol flow that can more closely simulate battlefield environment.

Abstract: The present application provides a memory device having word lines with improved resistance, and a manufacturing method of the memory device. The memory device includes a semiconductor substrate defined with a peripheral region and an array region at least partially surrounded by the peripheral region, and including a first recess extending into the semiconductor substrate and disposed in the array region; an isolation structure surrounded by the semiconductor substrate and disposed in the peripheral region; and a word line disposed within the first recess, wherein the word line includes an insulating layer conformal to the first recess and a conductive member surrounded by the insulating layer, and the conductive member includes a second recess extending into the conductive member and toward the semiconductor substrate. A method of manufacturing the memory device is also disclosed.

Abstract: Disclosed herein is a method for alleviating a chronic liver disease, comprising administrating to a subject in need thereof a pharmaceutical composition containing rosoxacin.

Abstract: A planar insulating spacer layer can be formed over a substrate, and a combination of a semiconducting material layer, a thin film transistor (TFT) gate dielectric layer, and a gate electrode can be formed over the planar insulating spacer layer. A dielectric matrix layer is formed thereabove. A source-side via cavity and a drain-side via cavity can be formed through the dielectric matrix layer over end portions of the semiconducting material layer. Mechanical stress can be generated between the end portions of the semiconducting material layer by changing a lattice constant of end portions of the semiconducting material layer. The mechanical stress can enhance the mobility of charge carriers in a channel portion of the semiconducting material layer.

Abstract: An image processing circuit for controlling a panel is configured to: receive information of a fixed pattern noise (FPN) corresponding to a first sensing zone of the panel, wherein the first sensing zone is determined according to a touch position of a finger; scan the first sensing zone to perform fingerprint sensing on the finger, to receive a plurality of raw sensing signals; remove the FPN from the plurality of raw sensing signals to generate a plurality of modified sensing signals; and output a plurality of fingerprint data to a host for fingerprint recognition, wherein the plurality of fingerprint data are converted from the plurality of modified sensing signals.

Abstract: A memory structure includes: first and second word lines; a high-k dielectric layer disposed on the first and second word lines; a channel layer disposed on the high-k dielectric layer and comprising a semiconductor material; first and second source electrodes electrically contacting the channel layer; a first drain electrode disposed on the channel layer between the first and second source electrodes; a memory cell electrically connected to the first drain electrode; and a bit line electrically connected to the memory cell.