Patents by Inventor Jung Yu

Jung Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12070833
    Abstract: A method of using a polishing pad includes applying a slurry to a first location on the polishing pad. The method further includes rotating the polishing pad. The method further includes spreading the slurry across a first region of the polishing pad at a first rate, wherein the first region includes a plurality of first grooves. The method further includes spreading the slurry across a second region, surrounding the first region of the polishing pad at a second rate different from the first rate, wherein the second region includes a plurality of second grooves. The method further includes spreading the slurry across a third region, surrounding the second region of the polishing pad at a third rate less than the first rate and the second rate, wherein the third region includes a plurality of third grooves.
    Type: Grant
    Filed: June 26, 2023
    Date of Patent: August 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chunhung Chen, Jung-Yu Li, Sheng-Chen Wang, Shih-Sian Huang
  • Patent number: 12074219
    Abstract: A disclosed semiconductor device includes a substrate, a gate electrode formed on the substrate, a gate dielectric layer formed over the gate electrode, a source electrode located adjacent to a first side of the gate electrode, and a drain electrode located adjacent to a second side of the gate electrode. A gate dielectric formed from an etch-stop layer and/or high-k dielectric layer separates the source electrode from the gate electrode and substrate and separates the drain electrode from the gate electrode and the substrate. First and second oxide layers are formed over the gate dielectric and are located adjacent to the source electrode on the first side of the gate electrode and located adjacent to the drain electrode on the second side of the gate electrode. A semiconductor layer is formed over the first oxide layer, the second oxide layer, the source electrode, the drain electrode, and the gate dielectric.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: August 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yong-Jie Wu, Yen-Chung Ho, Hui-Hsien Wei, Chia-Jung Yu, Pin-Cheng Hsu, Feng-Cheng Yang, Chung-Te Lin
  • Publication number: 20240282770
    Abstract: A memory device including bit lines, auxiliary lines, selectors, and memory cells is provided. The word lines are intersected with the bit lines. The auxiliary lines are disposed between the word lines and the of bit lines. The selectors are inserted between the bit lines and the auxiliary lines. The memory cells are inserted between the word lines and the auxiliary lines.
    Type: Application
    Filed: April 23, 2024
    Publication date: August 22, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Jung Yu, Pin-Cheng Hsu
  • Publication number: 20240276701
    Abstract: The present application provides a method for manufacturing a memory device having word lines with improved resistance, and a manufacturing method of the memory device. The method includes providing a semiconductor substrate defined with a peripheral region and an array region at least partially surrounded by the peripheral region; forming a first recess extending into the semiconductor substrate and disposed in the array region; and forming a word line disposed within the first recess. The formation of the word line includes disposing an insulating layer conformal to the first recess, and forming a conductive member surrounded by the insulating layer and having a second recess extending into the conductive member and toward the semiconductor substrate.
    Type: Application
    Filed: April 17, 2024
    Publication date: August 15, 2024
    Inventor: JUNG-YU WU
  • Publication number: 20240266414
    Abstract: Embodiments of the disclosure advantageously provide methods of manufacturing semiconductor devices having multi-Vt capability in the scaled space between nanosheets in advanced GAA nodes. One or more embodiments provide an integration scheme to advantageously reduce the gate resistance by combining n-/p-dipole and mid-gap metal with low resistance to achieve desired work function and low-resistance metal gate. In one or more embodiments, a mid-gap metal is used to fill nanosheets and act as a liner for subsequent fill by a low resistance metal. After dipole engineering, instead of filling the gate-all-around nanosheet with traditional n or p metal, in one or more embodiments, the nanosheet is advantageously filled with a single work function mid-gap metal to achieve n and p work function. If the work function was shifted in either P-dipole or N-dipole bandedge after dipole engineering, the mid-gap materials can also shift the bandedge the opposite way.
    Type: Application
    Filed: March 22, 2023
    Publication date: August 8, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Srinivas Gandikota, Yixiong Yang, Tengzhou Ma, Tianyi Huang, Geetika Bajaj, Hsin-Jung Yu, Seshadri Ganguli
  • Patent number: 12058873
    Abstract: A semiconductor device includes a semiconducting metal oxide fin located over a lower-level dielectric material layer, a gate dielectric layer located on a top surface and sidewalls of the semiconducting metal oxide fin, a gate electrode located on the gate dielectric layer and straddling the semiconducting metal oxide fin, an access-level dielectric material layer embedding the gate electrode and the semiconducting metal oxide fin, a memory cell embedded in a memory-level dielectric material layer and including a first electrode, a memory element, and a second electrode, and a bit line overlying the memory cell. The first electrode may be electrically connected to a drain region within the semiconducting metal oxide fin through a first electrically conductive path, and the second electrode is electrically connected to the bit line.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: August 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yong-Jie Wu, Yen-Chung Ho, Hui-Hsien Wei, Chia-Jung Yu, Pin-Cheng Hsu, Mauricio Manfrini, Chung-Te Lin
  • Publication number: 20240260468
    Abstract: An organic electroluminescent device including a first electrode, a second electrode, and an organic layer formed between the first electrode and the second electrode. The organic layer includes a light emitting layer formed using a solution containing an organic electroluminescent material and a solvent. The organic electroluminescent material includes a host and a dopant, and the host is one or more compounds represented by [Formula A] below.
    Type: Application
    Filed: December 19, 2023
    Publication date: August 1, 2024
    Inventors: Soon Wook Cha, Ji Won Lee, Tae Jung Yu, Yong Woon Yang
  • Publication number: 20240243050
    Abstract: A semiconductor package includes a package substrate, an interposer disposed on the package substrate, and a first semiconductor chip disposed on the interposer. The interposer includes a first semiconductor substrate and a first dielectric layer disposed on the first semiconductor substrate. The first dielectric layer includes a first scribe lane region. The first scribe lane region is below the first semiconductor chip along a first direction that is perpendicular to a top surface of the first semiconductor substrate. The first scribe lane region is spaced apart from a lateral surface of the interposer.
    Type: Application
    Filed: November 7, 2023
    Publication date: July 18, 2024
    Inventor: HAE-JUNG YU
  • Publication number: 20240237383
    Abstract: An organic electroluminescent device including a first electrode, a second electrode, and an organic layer formed between the first electrode and the second electrode. The organic layer includes a light emitting layer formed using a solution containing an organic electroluminescent material and a solvent. The organic electroluminescent material includes a host and a dopant, and the host is one or more compounds represented by [Formula A] below.
    Type: Application
    Filed: December 19, 2023
    Publication date: July 11, 2024
    Inventors: Soon Wook Cha, Ji Won Lee, Tae Jung Yu, Yong Woon Yang
  • Publication number: 20240237384
    Abstract: An organic electroluminescent device including a first electrode, a second electrode, and an organic layer formed between the first electrode and the second electrode. The organic layer includes a light emitting layer formed using a solution containing an organic electroluminescent material and a solvent. The organic electroluminescent material includes a host and a dopant, and the host is one or more compounds represented by [Formula A] below.
    Type: Application
    Filed: December 19, 2023
    Publication date: July 11, 2024
    Inventors: Soon Wook Cha, Ji Won Lee, Tae Jung Yu, Yong Woon Yang
  • Publication number: 20240224537
    Abstract: A thin film transistor includes an active layer located over a substrate, a first gate stack including a stack of a first gate dielectric and a first gate electrode and located on a first surface of the active layer, a pair of first contact electrodes contacting peripheral portions of the first surface of the active layer and laterally spaced from each other along a first horizontal direction by the first gate electrode, a second contact electrode contacting a second surface of the active layer that is vertically spaced from the first surface of the active layer, and a pair of second gate stacks including a respective stack of a second gate dielectric and a second gate electrode and located on a respective peripheral portion of a second surface of the active layer.
    Type: Application
    Filed: March 19, 2024
    Publication date: July 4, 2024
    Inventors: Yong-Jie Wu, Hui-Hsien Wei, Yen-Chung HO, Chia-Jung Yu, Chung-Te Lin, Feng-Cheng Yang, Pin-Cheng Hsu
  • Publication number: 20240222195
    Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices which meet reduced thickness, lower thermal budget, and Vt requirements, and have improved device performance and reliability. Advantageously, the embodiments of the present disclosure provide methods of manufacturing electronic devices that achieve desired dipole effect without an annealing process. To achieve desired dipole effect that is “thinner” than 3 ?, embodiments of the disclosure advantageously include methods of controlling surface adsorption equilibrium and, in turn, controlling the fraction of substrate surface atomic sites that are occupied by dipole species, which is not considered to be achievable by ALD processes.
    Type: Application
    Filed: February 13, 2023
    Publication date: July 4, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Tianyi Huang, Srinivas Gandikota, Yixiong Yang, Tengzhou Ma, Steven C.H. Hung, Hsin-Jung Yu, Geetika Bajaj
  • Patent number: 12027584
    Abstract: A transistor structure including a substrate, a gate structure, first pocket doped regions, second pocket doped regions, and source/drain extension regions, and source/drain regions is provided. The gate structure is located on the substrate. The first pocket doped regions are located in the substrate aside the gate structure. A dopant of the first pocket doped region includes a group IVA element. The second pocket doped regions are located in the substrate aside the gate structure. A depth of the second pocket doped region is greater than a depth of the first pocket doped region. The source/drain extension regions are located in the first pocket doped regions. The source/drain regions are located in the substrate aside the gate structure. The source/drain extension region is located between the source/drain region and the gate structure.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: July 2, 2024
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Jeng Hwa Liao, Zong-Jie Ko, Hsing-Ju Lin, Jung-Yu Shieh, Ling-Wuu Yang
  • Publication number: 20240207245
    Abstract: A method for inhibiting the metastasis of triple-negative breast cancer, which includes administering to a subject in need thereof a pharmaceutical composition containing rosoxacin or a pharmaceutically acceptable salt thereof.
    Type: Application
    Filed: June 6, 2023
    Publication date: June 27, 2024
    Inventors: Jinn-Moon YANG, Chia-Hwa LEE, Jung-Yu LEE, Yun-Ti CHEN
  • Patent number: 11998541
    Abstract: Disclosed herein is a method for alleviating a chronic liver disease, comprising administrating to a subject in need thereof a pharmaceutical composition containing rosoxacin.
    Type: Grant
    Filed: November 11, 2022
    Date of Patent: June 4, 2024
    Assignee: National Yang Ming Chiao Tung University
    Inventors: Jinn-Moon Yang, Shey-Cherng Tzou, Ming-Lung Yu, Yun-Ti Chen, Hsiao-Chen Huang, Jung-Yu Lee
  • Patent number: 11996405
    Abstract: A memory device including bit lines, auxiliary lines, selectors, and memory cells is provided. The word lines are intersected with the bit lines. The auxiliary lines are disposed between the word lines and the of bit lines. The selectors are inserted between the bit lines and the auxiliary lines. The memory cells are inserted between the word lines and the auxiliary lines.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Jung Yu, Pin-Cheng Hsu
  • Publication number: 20240139688
    Abstract: A polymeric hollow fiber membrane is provided having a crosslinked selective layer formed by sequentially performing coating of a polymer precursor on a crosslinked polymeric hollow fiber membrane support and thermal condensation and thermal crosslinking thereof, a carbon molecular sieve hollow fiber membrane, methods for producing the same, and methods of separating gases using the same. The polymeric hollow fiber membrane and the carbon molecular sieve hollow fiber membrane each have a thin crosslinked selective layer and excellent plasticization resistance and separation performance. Accordingly, the polymeric hollow fiber membrane and the carbon molecular sieve hollow fiber membrane, each of which has a thin crosslinked selective layer, can be effectively used in the separation of a mixed gas.
    Type: Application
    Filed: October 4, 2023
    Publication date: May 2, 2024
    Inventors: Jong Suk LEE, Hyun Jung YU, Heseong AN, Ju Ho SHIN
  • Patent number: 11968840
    Abstract: A thin film transistor includes an active layer located over a substrate, a first gate stack including a stack of a first gate dielectric and a first gate electrode and located on a first surface of the active layer, a pair of first contact electrodes contacting peripheral portions of the first surface of the active layer and laterally spaced from each other along a first horizontal direction by the first gate electrode, a second contact electrode contacting a second surface of the active layer that is vertically spaced from the first surface of the active layer, and a pair of second gate stacks including a respective stack of a second gate dielectric and a second gate electrode and located on a respective peripheral portion of a second surface of the active layer.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yong-Jie Wu, Yen-Chung Ho, Hui-Hsien Wei, Chia-Jung Yu, Pin-Cheng Hsu, Feng-Cheng Yang, Chung-Te Lin
  • Patent number: 11935867
    Abstract: A semiconductor package comprising a package substrate that extends in a first direction and a second direction perpendicular to the first direction, a plurality of logic dies and a memory stack structure on the package substrate, and an interposer substrate mounted in the package substrate. The memory stack structure vertically overlaps the interposer substrate. Each of the logic dies includes a first part that is horizontally offset from the interposer substrate and a second part that vertically overlaps the interposer substrate. The interposer substrate includes an interlayer dielectric layer and a plurality of wiring lines in the interlayer dielectric layer. The memory stack structure is electrically connected to at least one of the logic dies through the wiring lines of the interposer substrate.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: March 19, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yanggyoo Jung, Sungeun Kim, Sangmin Yong, Hae-Jung Yu
  • Publication number: 20240053247
    Abstract: The present invention provides a practical protection performance test evaluation technology of CBRN protective clothing according to mass transfer characteristics of an aerosol, which is to break away from the existing static CBRN protection test cell and reflect an air flow around the CBRN protection and body motions of individual soldiers, and dynamically design a Swatch test cell in a geometric shape that can be installed inside a wind tunnel, and reflect an aerosol flow that can more closely simulate battlefield environment.
    Type: Application
    Filed: August 8, 2023
    Publication date: February 15, 2024
    Inventors: Seung Jung YU, Hyun Sook JUNG, Hee Soo JUNG, Goon Hyeok KIM, Jae Heon LEE