Abstract: The fingerprint sensing device that includes a first analog front end (AFE) circuit, a compensation circuit, a correction circuit and an output circuit is introduced. The AFE circuit generates a first image signal according to the fingerprint data read from the plurality of rows of the fingerprint sensor. The correction circuit receives a first output digital code that is generated by reading a predetermined row among the plurality of rows of the fingerprint sensor, and calculates a brightness correction value and a relative illumination (RI) correction value according to the first output digital code. The compensation circuit modifies the first image signal according to the brightness correction value and the RI correction value to generate a second image signal. The output circuit is configured to generate a second output digital code according to the second image signal.

Abstract: A digital printed fabric includes a base cloth and a digital printing ink disposed on the base cloth, and a manufacturing method for the digital printing ink includes the following steps. A first thermal process including mixing a dye, a crosslinking agent, and a polyol is performed, such that a polymer dye is formed, in which a reaction temperature of the first thermal process is between 70° C. and 90° C. A second thermal process including mixing the polymer dye and an aqueous bridging agent is performed, such that a first mixture is formed, in which a reaction temperature of the second thermal process is between 90° C. and 120° C. A third thermal process including mixing the first mixture and a chain extender is performed, such that the digital printing ink is formed, in which a reaction temperature of the third thermal process is between 120° C. and 150° C.

Abstract: The present application discloses a flow speed detection circuit and a related chip and flow meter. The flow speed detection circuit includes: a transmitter, configured to provide a front signal and a main signal to a first transducer, wherein the first transducer transforms the front signal and the main signal into a transduced signal to a second transducer, the second transducer transforms the transduced signal into a receiving front signal and a receiving main signal to a receiver; and the receiver includes: a front signal detection circuit, configured to enable the main signal processing circuit after the receiving front signal; and the main signal processing circuit, configured to determine the flow speed based on the receiving main signal after being enabled.

Abstract: A hybrid crosslinked polymeric membrane and a process for fabricating the same are provided. Specifically, the hybrid crosslinked polymer membrane comprises a glassy polymer and a ladder-structured polysilsesquioxane and has a crosslinked structure. The hybrid crosslinked polymer membrane can have an excellent permeability of carbon dioxide by virtue of an increase in the free volume and enhanced plasticization resistance, chemical resistance, and durability.

Abstract: A method includes supplying slurry onto a polishing pad; holding a wafer against the polishing pad with a piezoelectric layer interposed vertically between a pressure unit and the wafer; exerting a force on the piezoelectric layer using the pressure unit to make the piezoelectric layer directly press the wafer; generating, using the piezoelectric layer, a first voltage corresponding to a first portion of the wafer and a second voltage corresponding to a second portion of the wafer; tuning the force exerted on the piezoelectric layer according to the first voltage and the second voltage; and polishing, using the polishing pad, the wafer.

Abstract: A disclosed method of fabricating a semiconductor structure includes forming a first conductive pattern over a substrate, with the first conductive pattern including a first conductive line and a second conductive line. A barrier layer may be conformally formed over the first conductive line and the second conductive line of the first conductive pattern. An insulating layer may be formed over the barrier layer. The insulating layer may be patterned to form openings between conductive lines of the first conductive pattern a second conductive pattern may be formed in the openings. The second conductive pattern may include a third conductive line is physically separated from the first conductive pattern by the barrier layer. The presence of the barrier layer reduces the risk of a short circuit forming between the first and second conductive patterns. In this sense, the second conductive pattern may be self-aligned relative to the first conductive pattern.

Abstract: A disclosed semiconductor device includes a substrate, a gate electrode formed on the substrate, a gate dielectric layer formed over the gate electrode, a source electrode located adjacent to a first side of the gate electrode, and a drain electrode located adjacent to a second side of the gate electrode. A gate dielectric formed from an etch-stop layer and/or high-k dielectric layer separates the source electrode from the gate electrode and substrate and separates the drain electrode from the gate electrode and the substrate. First and second oxide layers are formed over the gate dielectric and are located adjacent to the source electrode on the first side of the gate electrode and located adjacent to the drain electrode on the second side of the gate electrode. A semiconductor layer is formed over the first oxide layer, the second oxide layer, the source electrode, the drain electrode, and the gate dielectric.

Abstract: A method for fingerprint recognition and a fingerprint recognition device are provided. The method includes the following steps. A touch position of a touch panel is obtained as a fingerprint position. A fingerprint recognition operation is performed according to the fingerprint position. Whether the fingerprint recognition operation is successful is determined. In response to determining that the fingerprint recognition operation is not successful, at least one first position of the touch panel as an updated fingerprint position is generated according to the touch position of the touch panel, and the fingerprint recognition operation is performed according to the updated fingerprint position.

Abstract: A thin film transistor includes an active layer located over a substrate, a first gate stack including a stack of a first gate dielectric and a first gate electrode and located on a first surface of the active layer, a pair of first contact electrodes contacting peripheral portions of the first surface of the active layer and laterally spaced from each other along a first horizontal direction by the first gate electrode, a second contact electrode contacting a second surface of the active layer that is vertically spaced from the first surface of the active layer, and a pair of second gate stacks including a respective stack of a second gate dielectric and a second gate electrode and located on a respective peripheral portion of a second surface of the active layer.

Abstract: A semiconductor package includes a first semiconductor chip that has a mount region and an overhang region, a substrate disposed on a bottom surface at the mount region of the first semiconductor chip, and a molding layer disposed on the substrate. The molding layer includes a first molding pattern disposed on a bottom surface at the overhang region of the first semiconductor chip and covering a sidewall of the substrate, and a second molding pattern on the first molding pattern and covering a sidewall of the first semiconductor chip.

Abstract: An apparatus and method for orthogonal frequency division multiplexing (OFDM) transmission in a wireless local area network (WLAN) system is disclosed, in which the apparatus for OFDM transmission in the WLAN system includes a signal repetition unit to repeat an encoded signal based on a block unit and output the encoded signal and a repeated signal, an interleaver to interleave the encoded signal and the repeated signal and output an interleaved signal, a modulator to modulate the interleaved signal and output modulated symbols, and a phase rotation unit to phase shift the modulated symbol.

Abstract: A hole puncher is provided, including: a frame, including a base and a guide portion, the base including at least one punching hole, the guide portion including at least one guide hole corresponding to the at least one punching hole, there being a distance between the punching hole and the guide hole; an operating lever, provably connected to the frame; at least one punching rod, driven by the operating lever, being relatively movable within the at least one guide hole and movable to come within or out from the at least one punching hole, each punching rod including a first straight section, a second straight section and a tapered section which is tapered from the first straight section toward the second straight section.

Abstract: The present application discloses a signal processing circuit (100), coupled to a first transducer (102) and a second transducer (104), wherein there is a distance greater than zero between the first transducer and the second transducer, and a fluid having a flow velocity flows sequentially through the first transducer and the second transducer; the signal processing circuit includes: a first transmitter (106), coupled to the first transducer; a first receiver (108), coupled to the first transducer; a second transmitter (110), coupled to the second transducer; a second receiver (112), coupled to the second transducer; and a control unit (114), coupled to the first transmitter, the first receiver, the second transmitter and the second receiver. The present application further provides a related chip, a flow meter and a method.

Abstract: The present application discloses a signal processing circuit (100), coupled to a first transducer (102) and a second transducer (104), wherein the first transducer and the second transducer have a distance greater than zero, and a fluid having a flow velocity flows sequentially through the first transducer and the second transducer, the signal processing circuit includes: a first transmitter (106), coupled to the first transducer; a first receiver (108), coupled to the first transducer; a second transmitter (110), coupled to the second transducer; a second receiver (112), coupled to the second transducer; and a control unit (114), coupled to the first transmitter, the first receiver, the second transmitter and the second receiver. The present application further provides a related chip, a flow meter and a method.

Abstract: A method includes supplying slurry onto a polishing pad. A wafer is held against the polishing pad with a first piezoelectric layer interposed between a pressure unit and the wafer. A first voltage generated by the first piezoelectric layer is detected. The wafer is pressed, using the pressure unit, against the polishing pad according to the detected first voltage generated by the first piezoelectric layer. The wafer is polished using the polishing pad.

Abstract: A laser rangefinder, including: a housing; a first rotational mechanism, mounted to the housing, including a first shaft and a first driving device, the first driving device driving the first shaft to rotate about a first axial direction; a reflector, connected with the first shaft; a laser rangefinding module, mounted within the housing, including a transmitting module and a receiving module; a second rotational mechanism, mounted to the housing, including a second shaft and a second driving device, the second driving device driving the second shaft to rotate about a second axial direction, the first axial direction and the second axial direction being non-parallel; wherein the first shaft is configured to drive the reflector to rotate on a scan plane, the first rotational mechanism, the laser rangefinding module and the second rotational mechanism are located at a same side of the scan plane.

Abstract: An LDMOS device comprises a well region, first and second implant regions, a gate electrode, first and second source/drain regions, a first STI region, and a first DTI region. The well region is in a substrate and of a first conductivity type. The first implant region is in the substrate and of a second conductivity type. The second implant region is in the well region and of the first conductivity type. The gate electrode extends from above the well region to above the first implant region. The first and second source/drain regions are respectively in the first and second implant regions. The first STI region laterally extends from the second implant region to directly below the gate electrode. The first DTI region extends downwards from a bottom surface of the first STI region into the well region. The first DTI region vertically overlaps with the gate electrode.

Abstract: A semiconductor package comprising a package substrate that extends in a first direction and a second direction perpendicular to the first direction, a plurality of logic dies and a memory stack structure on the package substrate, and an interposer substrate mounted in the package substrate. The memory stack structure vertically overlaps the interposer substrate. Each of the logic dies includes a first part that is horizontally offset from the interposer substrate and a second part that vertically overlaps the interposer substrate. The interposer substrate includes an interlayer dielectric layer and a plurality of wiring lines in the interlayer dielectric layer. The memory stack structure is electrically connected to at least one of the logic dies through the wiring lines of the interposer substrate.

Abstract: A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the sec

Abstract: A pixel binning method for processing pixel data acquired from an image sensor comprising a pixel array, the pixel binning method includes performing a first scanning process that is to scan a sensing area of the image sensor, to obtain a first number of pixel data; performing a second scanning process that is to scan the sensing area after the first scanning process is completed, to obtain a second number of pixel data; performing pixel binning on the second number of pixel data according to an offset value and an arithmetic value, wherein the offset value is determined according to the first number of pixel data.