Abstract: A laser rangefinder, including: a housing; a first rotational mechanism, mounted to the housing, including a first shaft and a first driving device, the first driving device driving the first shaft to rotate about a first axial direction; a reflector, connected with the first shaft; a laser rangefinding module, mounted within the housing, including a transmitting module and a receiving module; a second rotational mechanism, mounted to the housing, including a second shaft and a second driving device, the second driving device driving the second shaft to rotate about a second axial direction, the first axial direction and the second axial direction being non-parallel; wherein the first shaft is configured to drive the reflector to rotate on a scan plane, the first rotational mechanism, the laser rangefinding module and the second rotational mechanism are located at a same side of the scan plane.

Abstract: An LDMOS device comprises a well region, first and second implant regions, a gate electrode, first and second source/drain regions, a first STI region, and a first DTI region. The well region is in a substrate and of a first conductivity type. The first implant region is in the substrate and of a second conductivity type. The second implant region is in the well region and of the first conductivity type. The gate electrode extends from above the well region to above the first implant region. The first and second source/drain regions are respectively in the first and second implant regions. The first STI region laterally extends from the second implant region to directly below the gate electrode. The first DTI region extends downwards from a bottom surface of the first STI region into the well region. The first DTI region vertically overlaps with the gate electrode.

Abstract: A semiconductor package comprising a package substrate that extends in a first direction and a second direction perpendicular to the first direction, a plurality of logic dies and a memory stack structure on the package substrate, and an interposer substrate mounted in the package substrate. The memory stack structure vertically overlaps the interposer substrate. Each of the logic dies includes a first part that is horizontally offset from the interposer substrate and a second part that vertically overlaps the interposer substrate. The interposer substrate includes an interlayer dielectric layer and a plurality of wiring lines in the interlayer dielectric layer. The memory stack structure is electrically connected to at least one of the logic dies through the wiring lines of the interposer substrate.

Abstract: A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the sec

Abstract: A pixel binning method for processing pixel data acquired from an image sensor comprising a pixel array, the pixel binning method includes performing a first scanning process that is to scan a sensing area of the image sensor, to obtain a first number of pixel data; performing a second scanning process that is to scan the sensing area after the first scanning process is completed, to obtain a second number of pixel data; performing pixel binning on the second number of pixel data according to an offset value and an arithmetic value, wherein the offset value is determined according to the first number of pixel data.

Abstract: A moisture-sensed shrinking ink applied to a digital printing process for fabric has a viscosity between 2.5 cP and 10.0 cP and a surface tension between 22 dyne/cm and 32 dyne/cm, in which the moisture-sensed shrinking ink includes 15 parts by weight to 35 parts by weight of a moisture-sensed shrinking resin and 65 parts by weight to 85 parts by weight of water.

Abstract: The present disclosure provides a moisture-sensed deforming fabric which includes a base cloth and a moisture-sensed shrinking ink. The moisture-sensed shrinking ink is jetted on one of surfaces of the base cloth by a digital printing process, and the moisture-sensed shrinking ink forms a hydrophilic region on the surface of the base cloth.

Abstract: The application discloses a signal generation circuit (100), configured to generate a transmission signal to trigger a first transducer to generate a first transducer output signal; the signal generation circuit includes: a signal generation unit (106), configured to generate an output signal; and a transmitter (104), coupled to the signal generation unit, wherein the transmitter is configured to convert the output signal into the transmission signal; wherein the transmission signal includes a data signal and a compensation signal, the data signal includes at least one first pulse wave, the compensation signal includes at least one second pulse wave, the first pulse wave and the second pulse wave have opposite phases, and the first pulse wave has an other waveform parameter different from an other waveform parameter of the second pulse wave. The present application further provides a related chip, a flow meter and a method.

Abstract: An objective of the invention is to provide an organic EL device that combines various materials of the device and a capping layer composed from a material that absorbs sunlight within the wavelength range of 400 nm to 410 nm to prevent impact on materials inside the organic EL device, has a high light absorption coefficient and a high refractive index to significantly improve light extraction efficiency, has excellent stability, durability and light resistance in a thin film, and has no absorption within the wavelength ranges of blue, green and red, to thereby effectively achieve the characteristics of the various materials of the device. The invention is an arylamine compound having a benzazole structure, and is also an organic EL device including a capping layer containing the arylamine compound and a light-emitting layer containing a host and a phosphorescent dopant.

Abstract: A method for processing a bet on a sports game includes: generating and displaying a first betting page for user interaction, the first betting page allowing selection of a time instance associated with a sports game; in response to receipt of user-input content indicating the selection of the time instance, generating and displaying a second betting page for user interaction, the second betting page allowing selection of an outcome associated with the time instance of the sports game; and in response to receipt of a bet that indicates the selection of the outcome associated with the time instance of the sports game, determining a result of the bet based on a result of the sports game at the time instance.

Abstract: A planar insulating spacer layer can be formed over a substrate, and a combination of a semiconducting material layer, a thin film transistor (TFT) gate dielectric layer, and a gate electrode can be formed over the planar insulating spacer layer. A dielectric matrix layer is formed thereabove. A source-side via cavity and a drain-side via cavity can be formed through the dielectric matrix layer over end portions of the semiconducting material layer. Mechanical stress can be generated between the end portions of the semiconducting material layer by changing a lattice constant of end portions of the semiconducting material layer. The mechanical stress can enhance the mobility of charge carriers in a channel portion of the semiconducting material layer.

Abstract: A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the sec

Abstract: An operating mode change method of a wireless local area network (WLAN) system according to an exemplary embodiment includes transmitting, by a station (STA) to an access point (AP), an operating mode change request frame comprising at least one of information on a change of a traffic indication map (TIM) mode, a request for a change of a power save parameter, and information on a change of a service type of the STA, receiving, from the AP, an operating mode change response frame comprising at least one of a TIM mode allowed by the AP, a reallocated association identification (AID), and information on a changed power save parameter, and performing at least one of the change of the TIM mode and the change of the power save parameter based on the information included in the operating mode change.

Abstract: A method and an apparatus for allocating a flexible transmission slot in a wireless local area network (LAN) system are disclosed. A flexible transmission slot allocation method of an access point (AP) in a wireless local area network (WLAN) system according to an exemplary embodiment includes transmitting a beacon including a traffic indication map (TIM) bit to a station, receiving a power save poll (PS-Poll) from the station in a slot implicitly allocated by the TIM bit, and transmitting an acknowledgement (ACK) including transmission slot allocation information on downlink data to the station.

Abstract: The present invention relates to a terminal for requesting and acquiring information relating to channel access in a wireless LAN, and to an apparatus for providing information relating to channel access in a wireless LAN. The terminal for requesting and acquiring information relating to channel access in a wireless LAN according to one embodiment of the invention verifies the reception of a beacon during a preset beacon interval, if it is verified that the beacon has not been received, transmits a group and slot information request signal, and receives, from an access point, a group and slot information response signal as a response to the group and slot information request signal.

Abstract: A scanning method performed by a station (STA) in a wireless LAN system is provided. The method comprises: transmitting a probe request frame; and receiving a short probe response frame from an access point (AP) as a response to the probe request frame. The short probe response frame includes service set ID (SSID) information or compressed SSID information of the AP.

Abstract: A semiconductor device includes a semiconducting metal oxide fin located over a lower-level dielectric material layer, a gate dielectric layer located on a top surface and sidewalls of the semiconducting metal oxide fin, a gate electrode located on the gate dielectric layer and straddling the semiconducting metal oxide fin, an access-level dielectric material layer embedding the gate electrode and the semiconducting metal oxide fin, a memory cell embedded in a memory-level dielectric material layer and including a first electrode, a memory element, and a second electrode, and a bit line overlying the memory cell. The first electrode may be electrically connected to a drain region within the semiconducting metal oxide fin through a first electrically conductive path, and the second electrode is electrically connected to the bit line.

Abstract: A memory structure includes: first and second word lines; a high-k dielectric layer disposed on the first and second word lines; a channel layer disposed on the high-k dielectric layer and comprising a semiconductor material; first and second source electrodes electrically contacting the channel layer; a first drain electrode disposed on the channel layer between the first and second source electrodes; a memory cell electrically connected to the first drain electrode; and a bit line electrically connected to the memory cell.

Abstract: A memory structure, device, and method of making the same, the memory structure including a surrounding gate thin film transistor (TFT) and a memory cell stacked on the GAA transistor. The GAA transistor includes: a channel comprising a semiconductor material; a source electrode electrically connected to a first end of the channel; a drain electrode electrically connected to an opposing second end of the channel; a high-k dielectric layer surrounding the channel; and a gate electrode surrounding the high-k dielectric layer. The memory cell includes a first electrode that is electrically connected to the drain electrode.

Abstract: A semiconductor device includes a first dielectric layer, a gate electrode embedded within the first dielectric layer, a layer stack including a gate dielectric layer, a channel layer including a semiconducting metal oxide material, and a second dielectric layer, and a source electrode and a drain electrode embedded in the second dielectric layer and contacting a respective portion of a top surface of the channel layer. A combination of the gate electrode, the gate dielectric layer, the channel layer, the source electrode, and the drain electrode forms a transistor. The total length of the periphery of a bottom surface of the channel layer that overlies the gate electrode is equal to the width of the gate electrode or twice the width of the gate electrode, and resputtering of the gate electrode material on sidewalls of the channel layer is minimized.