Abstract: Disclosed is a variable gain circuit, which operates in a region where the gain varies substantially exponentially with respect to a control voltage, having an operation region in which the gain varies substantially with an exponential function {(?{square root over (1?x)}??{square root over (2)})2+K}/{(?{square root over (1+x)}??{square root over (2)})2+K} where 0?K?1 and x is a variable corresponding to the control voltage. The denominator and the numerator of the above function are given by a first sum current and a second sum current, respectively. The first sum current is a sum of the drain current of a first transistor and a constant current, and the second sum current is a sum of the drain current of a second transistor and the constant current. The first and second transistors have sources grounded, having gates connected common and supplied with a bias voltage, and having back-gates supplied with control voltages differentially.

Abstract: Disclosed is a filter circuit with an order of three or more, comprising at least one means for amplifying an in-band signal, wherein the frequency response of the filter output has a desirable attenuation characteristic obtainable with the order of the filter circuit. The gain of the amplifying means is variably controlled.

Abstract: In a filter apparatus including a master circuit for receiving a reference frequency signal having a reference frequency to generate a control voltage and a slave gm-C filter formed by at least one operational transconductance amplifier and at least one capacitor where the operational transconductance amplifier of the slave gm-C filter is controlled by the control voltage to tune a cut-off frequency or center frequency of the slave gm-C filter, the master circuit is constructed by first and second gm-C filters each formed by at least one operational transconductance amplifier and at least one capacitor and having different frequency characteristics from each other, the first and second gm-C filters being adapted to receive the reference frequency signal, first and second amplitude detectors having inputs connected to outputs of the first and second gm-C filters, respectively, and a differential amplifier having an input connected to outputs of the first and second amplitude detectors and being adapted to ampl

Abstract: Disclosed is a variable gain circuit including a gain change region in which the gain is changed substantially exponentially as a function of a control voltage. The gain is changed in the gain change region substantially exponentially based on a function {(1+x)2+K}/{1?x}2+K}, where x is a control voltage and K is a parameter of K?1. The parameter K of the function is about equal to 0.21. The denominator and the numerator of the function are proportionate to driving currents of OTAs (operational transconductance amplifiers). Or, the denominator and the numerator of the above function are constituted by output currents of a MOS differential pair and a quadritail cell that includes four transistors driven by a common tail current. Outputs of two of the transistors, receiving a differential input voltage, are connected in common and outputs of the other two of the transistors, receiving the common mode voltage of the differential input voltage, are connected in common.

Abstract: Disclosed is a PLL circuit in which an output signal of a frequency oscillator (VCO or ICO), an oscillation frequency of which is controlled by an electrical signal, is supplied via a high pass filter (HPF) to one of input terminals of a phase detector, the other input terminal of which receives a reference frequency. An output signal of the phase detector is supplied to a loop filter which then outputs a DC component of the signal that controls the frequency oscillator as the electrical signal.

Abstract: Disclosed is a PLL circuit in which an AC signal with a predetermined frequency is supplied as an input signal to a phase shifter comprising an OTA and a capacitor, and a phase comparator that receives the input signal to the phase shifter and an output signal from the phase shifter outputs a signal corresponding to a phase difference between the input signals. Control is performed so that the phase difference given by the phase shifter becomes a constant value by changing a transconductance (gm) of at the OTA constituting the phase shifter, using an output voltage of an amplifier for amplifying a DC voltage of the output signal of the phase comparator as a control signal.

Abstract: Disclosed is a CMOS current mirror circuit including a first MOS transistor and a second MOS transistor constituting a current mirror, in which a drain of the first MOS transistor and a gate of the second MOS transistor are connected in common, a source of the first MOS transistor is directly grounded, and a gate of the first MOS transistor is connected to the drain of the first MOS transistor through a third MOS transistor which has a source connected to the drain of the first MOS transistor, a drain connected to the gate of the first MOS transistor, and a gate being biased. The source of the second MOS transistor is directly grounded. Current is input to the drain of the third MOS transistor. The drain current of the second MOS transistor is mirrored by cascode current mirror circuits. An output current is output from the source of a MOS transistor for conversion to a voltage by a circuit that receives the current which outputs a reference voltage.

Abstract: A data processing apparatus is provided for processing an image signal obtained from a solid-state image pickup device, in which a plurality of types of color filters are discretely provided on pixels, and a pixel to be interpolated and surrounding pixels thereof have image signals. The apparatus comprises an interpolation section for generating a missing color signal in the image signal of each pixel by interpolation using at least the image signals of the surrounding pixels among the image signals of the pixel to be interpolated and the surrounding pixels thereof. The interpolation section obtains an interpolation pattern, which is similar to a pattern of data values of the pixel to be interpolated and the surrounding pixels thereof, depending on uniformity and gradient of the image signals of the pixel to be interpolated and the surrounding pixels thereof, and performs interpolation depending on the interpolation pattern.

Abstract: Disclosed is a reference voltage generating circuit including first to third current-to-voltage converter circuits, a control circuit for exercising control so that the terminal voltage of the first current-to-voltage converter circuit is made equal to that of the second current-to-voltage converter circuit, and current mirror circuits for driving the first to third current-to-voltage converter circuits. A preset voltage of the third current-to-voltage converter circuit is used as a reference voltage. The first current-to-voltage converter circuit is composed of a diode. The second current-to-voltage converter circuit includes a plurality of parallel connected diodes, a resistor connected in parallel with the plural parallel connected diodes and a resistor connected in series with the parallel-connected diodes and the resistor. The third current-to-voltage converter circuit is composed of a resistor.

Abstract: Disclosed is a reference voltage circuit which includes control means for exercising control so as to equalize a divided voltage that is output from a first current-to-voltage converting circuit having a diode-connected MOS transistor and voltage-dividing resistors and a divided voltage that is output from a second current-to-voltage converting circuit having a diode-connected MOS transistor and voltage-dividing resistors; a first current mirror circuit having a non-linear input/output characteristic for supplying currents to the first and second current-to-voltage converting circuits, respectively; a second current mirror circuit having a linear input/output characteristic for outputting a current proportional to the value of the current supplied to the first current-to-voltage converting circuit; and a third current mirror circuit having a linear input/output characteristic for outputting a current proportional to the value of the current supplied to the second current-to-voltage converting circuit.

Abstract: Disclosed is a differential circuit including a first transistor pair including first and second transistors having gates for receiving a differential input signal; a second transistor pair including third and fourth transistors having gates for commonly receiving a common mode voltage of the differential input signal, having drains connected to drains of said first and second transistors, respectively, and having sources coupled together; a third transistor pair including fifth and sixth transistors having gates for receiving the differential input signal, and cascode-connected to said third and fourth transistors, respectively; and a fourth transistor pair including seventh and eighth transistors having gates for receiving the differential input signal in reverse phase, and cascode-connected to said fifth and sixth transistors, respectively; wherein coupled drains of the first and third transistors and coupled drains of the second and fourth transistors constitute a differential output pair; and sources of

Abstract: Disclosed is a phase shifting circuit that includes a PLL loop in which a reference frequency received is branched into first and second signals. The first signal becomes one input to a phase comparator and the second signal becomes another input to the phase comparator after being shifted in phase via a phase shifter. The output of the phase comparator is supplied to one input terminal of a differential amplifier via a low-pass filter. The amount of phase shift of the phase shifter is controlled by the output signal of the differential amplifier. The amount of phase shift of the phase shifter is decided by a reference voltage applied to another input terminal of the differential amplifier.

Abstract: Disclosed is a reference voltage generating circuit including first to third current-to-voltage converter circuits, a control circuit for exercising control so that the terminal voltage of the first current-to-voltage converter circuit is made equal to that of the second current-to-voltage converter circuit, and current mirror circuits for driving the first to third current-to-voltage converter circuits. A preset voltage of the third current-to-voltage converter circuit is used as a reference voltage. The first current-to-voltage converter circuit is composed of a diode. The second current-to-voltage converter circuit includes a plurality of parallel connected diodes, a resistor connected in parallel with the plural parallel connected diodes and a resistor connected in series with the parallel-connected diodes and the resistor. The third current-to-voltage converter circuit is composed of a resistor.

Abstract: Disclosed is a reference voltage generating circuit comprising a first reference current circuit including first and second current-to-voltage converting circuits, control means for exercising control in such a manner that prescribed output voltages of the first and second current-to-voltage converting circuits become equal, and a first current mirror circuit for supplying currents to respective ones of the first and second current-to-voltage converting circuits; a second reference current circuit having third and fourth current-to-voltage converting circuits, control means for exercising control in such a manner that prescribed output voltages of the third and fourth current-to-voltage converting circuits become equal, and a second current mirror circuit which has a linear input/output characteristic, for supplying currents to respective ones of the third and fourth current-to-voltage converting circuits; and means for outputting a difference current between output current of the first reference current circ

Abstract: Disclosed is a complex elliptic filter having an order of three or higher which receives two differential signals that differ in phase from each other by 90 degrees are applied and outputs two differential signals that differ in phase from each other by 90 degrees. The complex filter circuit has internally at least two circuit blocks that include a capacitor connected in series with a coupler (gyrator). The complex filter is a third-order inverse Chebychev filter having an equiripple stopband of 40-dB attenuation amount. Alternatively, the coupler (gyrator) between elliptic capacitors is removed. Alternatively, the elliptic capacitors are made substantially equal to the capacitor arranged in parallel therewith. Alternatively, the gm value of an OTA and the capacitance value are each in an integral ratio represented substantially by a geometric progression of 2.

Abstract: Disclosed is a reference voltage generating circuit comprising a first reference current circuit including first and second current-to-voltage converting circuits, control means for exercising control in such a manner that prescribed output voltages of the first and second current-to-voltage converting circuits become equal, and a first current mirror circuit for supplying currents to respective ones of the first and second current-to-voltage converting circuits; a second reference current circuit having third and fourth current-to-voltage converting circuits, control means for exercising control in such a manner that prescribed output voltages of the third and fourth current-to-voltage converting circuits become equal, and a second current mirror circuit which has a linear input/output characteristic, for supplying currents to respective ones of the third and fourth current-to-voltage converting circuits; and means for outputting a difference current between output current of the first reference current circ

Abstract: Disclosed is a reference voltage circuit which includes control means for exercising control so as to equalize a divided voltage that is output from a first current-to-voltage converting circuit having a diode-connected MOS transistor and voltage-dividing resistors and a divided voltage that is output from a second current-to-voltage converting circuit having a diode-connected MOS transistor and voltage-dividing resistors; a first current mirror circuit having a non-linear input/output characteristic for supplying currents to the first and second current-to-voltage converting circuits, respectively; a second current mirror circuit having a linear input/output characteristic for outputting a current proportional to the value of the current supplied to the first current-to-voltage converting circuit; and a third current mirror circuit having a linear input/output characteristic for outputting a current proportional to the value of the current supplied to the second current-to-voltage converting circuit.

Abstract: In a filter apparatus includes a master circuit receiving a reference frequency to generate a control voltage, and a slave gm-C filter for receiving an input voltage to generate an output voltage. The slave gm-C filter is controlled by the control voltage to adjust the cut-off frequency or center frequency of the slave gm-C filter. The master circuit is a PLL circuit including a phase shifter receiving a reference frequency signal to change the phase of the reference frequency signal, a phase comparator to generate a phase error signal, and a loop filter adapted for excluding an AC component signal from the phase error signal to generate a DC component thereof. As a result, this DC component signal is supplied as the control voltage to the phase shifter and the slave gm-C filter.

Abstract: A CMOS reference voltage circuit, preferably formed on a semiconductor integrated circuit, and outputting a reference voltage having a temperature-independent characteristic, comprises first and second diode-connected transistors (or diodes), respectively grounded and driven with two constant currents bearing a constant current ratio to each other, and a unit for amplifying a differential voltage of output voltages from the first and second transistors by a preset factor and for summing the amplified differential voltage to an output voltage of the first or second transistor.

Abstract: A flicker correction apparatus for correcting a flicker component of an image signal obtained by imaging an object using an imaging device is provided. The apparatus comprises an image average calculation section for calculating an average of the image signal, a flicker frequency calculation section for calculating a flicker frequency, a flicker data extraction section for extracting flicker data using the average of the image signal and the flicker frequency, a flicker determination section for determining the presence or absence of a flicker phenomenon using the flicker data, a flicker correction amount calculation section for calculating a flicker correction amount using the flicker data, and a flicker correction section for removing the flicker component of the image data using the flicker correction amount.