Patents by Inventor Katsunori Misaki

Katsunori Misaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150153881
    Abstract: A highly-reliable arrangement of a cover-integrated touch panel is provided that ensures that the sensor electrodes are properly connected with the lines. A touch panel (1) includes: a transparent substrate (10); a light-shielding film (11) provided on a portion of the substrate (10); a planarizing film (12) provided over the substrate (10) and the light-shielding film (11); a barrier film (13) provided over the planarizing film (12); a sensor electrode (14, 15) provided on the barrier film (13); a terminal (16) provided in a region that overlies the light-shielding film (11) in a plan view; and a line (171) for electrically connecting the sensor electrode (14, 15) with the terminal (16). The barrier film (13) includes a first inorganic film (131) located adjacent the planarizing film (12) and formed of an inorganic material and a second inorganic film (132) located on the first inorganic film (131) and formed of an inorganic material with a smaller refractive index than the first inorganic film.
    Type: Application
    Filed: June 28, 2013
    Publication date: June 4, 2015
    Inventor: Katsunori Misaki
  • Patent number: 9035302
    Abstract: This active-matrix substrate (100A) includes: a substrate (11); a TFT (10A) which is supported on the substrate and which includes a semiconductor layer (14), a gate electrode (12g), a source electrode (16S) and a drain electrode (16D); first and second transparent conductive layers (22, 24), at least one of which is electrically connected to the drain electrode of the TFT and has tensile stress; and a stack of inorganic insulating layers (23S1) which has been formed between the first and second transparent conductive layers. The stack includes a first inorganic insulating layer (23a1) with tensile stress and second and third inorganic insulating layers (23b1, 23c1) which have been formed so as to sandwich the first inorganic insulating layer between them and which have compressive stress. The stack as a whole has tensile stress.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: May 19, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Katsunori Misaki
  • Publication number: 20150053968
    Abstract: This semiconductor device (1000A) includes a TFT (100A) with an oxide semiconductor layer 9, a storage capacitor line (12), and a first transparent electrode (15) electrically connected to the storage capacitor line (12). The first transparent electrode (15) includes a portion which overlaps with a first connecting layer (8x) when viewed along a normal to a substrate (1). The portion that overlaps with the first connecting layer (8x) has a point symmetric shape of which a point of symmetry is located inside a contact hole (CH2) when viewed along a normal to the substrate (1). The first transparent electrode (15) is not in direct contact with the first connecting layer (8x). A portion of the first transparent electrode (15) is in direct contact with a second connecting layer (8x). The first connecting layer (8x) is in direct contact with the second connecting layer (19a).
    Type: Application
    Filed: March 11, 2013
    Publication date: February 26, 2015
    Inventors: Katsunori Misaki, Kunio Matsubara
  • Publication number: 20150048360
    Abstract: A semiconductor device includes a substrate, a TFT supported by the substrate, an auxiliary capacitor, a source wiring line, and a gate wiring line. The auxiliary capacitor has a first auxiliary capacitor electrode, a second auxiliary capacitor electrode, and a first insulating layer. When viewed from the direction normal to the substrate, the gate wiring line and the source wiring line overlap to form a gate-source intersection region in which the first insulating layer and a second insulating layer are formed. The distance between the first auxiliary capacitor electrode and the second auxiliary capacitor electrode is smaller than the distance between the gate wiring line and the source wiring line in the gate-source intersection region.
    Type: Application
    Filed: March 11, 2013
    Publication date: February 19, 2015
    Applicant: Sharp Kabushiki Kaisha
    Inventor: Katsunori Misaki
  • Publication number: 20150042903
    Abstract: Provided is a highly reliable configuration of a one glass solution touch panel, in which a sensor electrode and a wiring line can be reliably connected to each other. A touch panel (1) is provided with: an insulating substrate (10) having a sensing area (V) and a non-sensing area (P); sensor electrodes (11, 12), which are formed in the sensing area (P); terminals (13), which are formed in the non-sensing area (P); wiring lines (14), which electrically connect the sensor electrodes (11, 12) and the terminals (13); a light-shielding layer (171), which is formed to cover the non-sensing area (P); and a planarizing film (172), which is formed to cover the light-shielding layer (171). The planarizing film (172) is formed only in the non-sensing area (P).
    Type: Application
    Filed: January 9, 2013
    Publication date: February 12, 2015
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Katsunori Misaki
  • Publication number: 20140375909
    Abstract: A configuration of a touch panel having a terminal structure that enables stable connection between lines and terminals is obtained. A touch panel includes: an insulating substrate (10); a first electrode that is formed on the substrate (10) and extends in a first direction; a second electrode that is formed on the substrate (10) and extends in a second direction that crosses the first direction; a first insulating film (15) that insulates the first electrode and the second electrode from each other; a terminal (18) formed on the substrate (10); and a line (14) that electrically connects a respective one of the first and second electrodes with the terminal (18).
    Type: Application
    Filed: December 20, 2012
    Publication date: December 25, 2014
    Inventor: Katsunori Misaki
  • Publication number: 20140346504
    Abstract: This active-matrix substrate (100A) includes: a substrate (11); a TFT (10A) which is supported on the substrate and which includes a semiconductor layer (14), a gate electrode (12g), a source electrode (16S) and a drain electrode (16D); first and second transparent conductive layers (22, 24), at least one of which is electrically connected to the drain electrode of the TFT and has tensile stress; and a stack of inorganic insulating layers (23S1) which has been formed between the first and second transparent conductive layers. The stack includes a first inorganic insulating layer (23a1) with tensile stress and second and third inorganic insulating layers (23b1, 23c1) which have been formed so as to sandwich the first inorganic insulating layer between them and which have compressive stress. The stack as a whole has tensile stress.
    Type: Application
    Filed: December 18, 2012
    Publication date: November 27, 2014
    Applicant: Sharp Kabushiki Kaisha
    Inventor: Katsunori Misaki
  • Publication number: 20140320761
    Abstract: A conductive protective layer (2) is provided that is formed in the same layer as a first bridge electrode (104A) on a layer above metal wiring (102) across an interlayer insulating film (103) so that the conductive protective layer overlaps the metal wiring (102) in a plan view. A touch panel having improved reliability can therefore be provided without increasing manufacturing unit price.
    Type: Application
    Filed: August 30, 2012
    Publication date: October 30, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Katsunori Misaki
  • Patent number: 8872180
    Abstract: A production method for a liquid crystal display device having a plurality of thin film transistors (TFTs) including reflection sections disposed to correspond to a plurality of pixels includes: a step of forming on a substrate a metal layer having apertures; a step of forming a semiconductor layer on the metal layer; a step of forming a protection layer on the semiconductor layer; a step of forming a resist layer on the protection layer; a photolithography step of irradiating the resist layer with light through the metal layer to pattern the protection layer by photolithography technique; and a step of stacking a reflective layer on the patterned protection layer. A plurality of bumps are formed from the protection layer in the photolithography step, and a plurality of bumps corresponding to the plurality of bumps of the protection layer are formed on the reflective layer.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: October 28, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Katsunori Misaki
  • Publication number: 20140313442
    Abstract: An arrangement of a touch panel with improved sensitivity is provided. A touch panel (1) includes: an insulating substrate (10); a first light-shielding portion extending in a first direction; a second light-shielding portion extending in a second direction, the second direction crossing the first direction; a plurality of first insular electrodes (110) arranged in the first direction; a plurality of second insular electrodes (120) arranged in the second direction; a first metal film (141) in contact with the plurality of first insular electrodes (110) and extending in the first direction; a second metal film (152) in contact with the plurality of second insular electrodes (120) and extending in the second direction; and an insulating film (152) provided at least at a crossing of the first metal film (151) and the second metal film (152) as in a plan view for providing electrical insulation between the first metal film (151) and the second metal film (152).
    Type: Application
    Filed: December 17, 2012
    Publication date: October 23, 2014
    Applicant: Sharp Kabushiki Kaisha
    Inventor: Katsunori Misaki
  • Publication number: 20140240624
    Abstract: A configuration of a touch panel in which an electrode pattern is not readily visible is attained in the present invention. A touch panel (1) is provided with an insulating substrate (10), first island-shaped electrodes (121) formed on the substrate (10) and arranged in one direction, second island-shaped electrodes (111) formed on the substrate (10) and arranged in a direction intersecting the direction in which the first island-shaped electrodes (121) are arranged, a first connecting member (122) for connecting the first island-shaped electrodes (121), a metallic film (17) formed on the first connecting member (122), an insulating film (16) formed so as to completely cover the metallic film (17), and a second connecting member (112) for connecting the second island-shaped electrodes (111) over the insulating film (16).
    Type: Application
    Filed: September 27, 2012
    Publication date: August 28, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Katsunori Misaki
  • Publication number: 20140240623
    Abstract: Provided is a touch panel configured to minimize electrode disconnection caused by swelling of the insulating layer during the production process. The touch panel is equipped with: an insulating substrate; first island-shaped electrodes (111) disposed along a first direction; second island-shaped electrodes (121) disposed along a second direction intersecting the first direction; a connecting member (112) for connecting together the first island-shaped electrodes (111); an insulating film (15) formed covering a portion of the connecting member (112); and a relay electrode (122) for connecting together the second island-shaped electrodes (121) over the insulating film (15). The relay electrode (122), in a section thereof that overlaps the connecting member (112) in a plan view, is narrower in width, in a direction perpendicular to the second direction, than the width of the insulating film (15).
    Type: Application
    Filed: September 21, 2012
    Publication date: August 28, 2014
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Kunio Matsubara, Katsunori Misaki
  • Publication number: 20140211111
    Abstract: The objective of the present invention is to achieve a manufacturing method that, in a capacitive touch panel, prevents the occurrence of residue in an electrode film caused by an etching defect for a touch panel in which electrode patterns are difficult to recognize. The manufacturing method for the touch panel includes: an electrode formation step for forming, upon an insulating substrate (10), first electrodes (11) and second electrodes (12) that extend in mutually intersecting directions; an insulating film formation step for forming insulating films (16) which cover portions of the insulating substrate (10), the first electrodes (11), and the second electrodes (12); and a bridge formation step for forming bridges (17) that connect neighboring second electrodes (12) together over the insulating films (16). In addition, before the bridge formation step, a surface treatment step for etching the surface of the first electrodes (11) and the second electrodes (12) is performed one or more times.
    Type: Application
    Filed: August 29, 2012
    Publication date: July 31, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Katsunori Misaki
  • Patent number: 8791463
    Abstract: Gate electrodes, a gate insulating layer, and an oxide semiconductor layer are simultaneously formed to form a multilayer structure, so that an SOG film serves as an etching stopper on channel regions in forming source electrodes and drain electrodes. In the SOG film, channel isolation holes are formed in positions each of which is located between adjacent two of TFTs connected to a common one of the gate lines, and corresponds to the common gate line. The oxide semiconductor layer of the adjacent TFTs is divided in each channel isolation hole. Terminal sections of the gate lines are exposed in the terminal section exposing holes formed in positions each corresponding to a gate line end portion. The pixel electrode is made of a film identical to a film forming one layer included in the drain electrode.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: July 29, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Katsunori Misaki
  • Patent number: 8780312
    Abstract: A liquid crystal panel (1) includes (i) a CF substrate (2) on which a color filter is to be formed, (ii) a TFT substrate (3) on which a thin film transistor is to be formed, (iii) a sealing material (4) for sealing liquid crystal injected between the CF substrate (2) and the TFT substrate (3), (iv) a liquid crystal inlet (6) through which the liquid crystal is injected, and (v) structures (20) provided between a cut surface among cut surfaces of the liquid crystal panel (1), on which cut surface the liquid crystal inlet (6) is to be formed, and edges (4a) of the sealing material (4). The structures (20) each are made from a material from which the color filter is formed.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: July 15, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shota Makimoto, Katsunori Misaki
  • Patent number: 8709265
    Abstract: Provided is a touch panel manufacturing method wherein the number of exposure masks needed for pattern formation is reduced, and a method for manufacturing a display device provided with a touch panel. A transparent conductive film layer (11) and a metal layer (12) are laminated on a transparent substrate (1), and the transparent conductive film layer (11) and the metal layer (12) are formed into predetermined electrode patterns, with use of one resist pattern. A protective film (13) covering the transparent conductive film layer (11) and the metal layer (12) is formed, and openings (14, 15, and 16) are provided at predetermined positioned in the protective film (13). By etching with use of the protective film (13) having the openings (14, 15, and 16), the metal layer (12) is removed so that the transparent conductive film layer (11) is exposed, whereby at least either touch electrodes (2) or connection terminals (5) are formed.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: April 29, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Katsunori Misaki
  • Patent number: 8698153
    Abstract: The TFT substrate (100A) in the present invention includes a thin film transistor, a gate line (3a), a source line (13as), and first and second terminals (40a, 40b) for electrically connecting the thin film transistor to an external wiring which are formed on a substrate (1). The first terminal includes a first gate terminal portion (41a) and a first pixel electrode line (29a). The first pixel electrode line is in contact with the first gate terminal portion in a first opening portion (27c) provided in an insulating film (5), and covers an end face of the insulating film in the first opening portion. The second terminal includes a second gate terminal portion (41b) and a second pixel electrode line (29b). The second pixel electrode line is in contact with the second gate terminal portion in a second opening portion (27d) provided in the insulating film, and covers an end face of the insulating film in the second opening portion.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: April 15, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Katsunori Misaki
  • Publication number: 20140042439
    Abstract: An active matrix substrate (1) includes a source electrode (32), a drain electrode (33), and a semiconductor layer (31) of oxide semiconductor. A gate insulating layer (42) of silicon oxide is formed on the gate electrode (12a); a source electrode (32), a drain electrode (33), and a semiconductor layer (31) are formed on the gate insulating layer (42); a first protection layer (44) of silicon nitride is formed on the gate insulating layer (42) without covering the semiconductor layer (31); and a second protection layer (46) of silicon oxide is formed on the semiconductor layer (31). The first protection layer (44) covers the signal line (14) and the source connection line (36).
    Type: Application
    Filed: March 22, 2012
    Publication date: February 13, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Katsunori Misaki
  • Publication number: 20140020944
    Abstract: There is provided a wiring connection structure connecting a transparent conductive film formed on a main surface of a transparent substrate having the main surface and a metal wiring formed on the main surface and made of a metal material, wherein the metal wiring is formed to extend from the main surface onto the transparent conductive film and to cover the transparent conductive film.
    Type: Application
    Filed: April 2, 2012
    Publication date: January 23, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Katsunori Misaki
  • Publication number: 20130314626
    Abstract: A drive substrate, including: an insulating substrate (10); an internal connection terminal (12b) made of ITO or IZO provided on the substrate (10); and a lead interconnect (14) that is connected to the connection terminal (12b) with one end thereof lying on the connection terminal and is led out to an outer edge of the insulating substrate (10) at the other end thereof, wherein a contact portion of the lead interconnect (14) with the internal connection terminal (12b) is formed of a barrier metal layer (15A) made of titanium nitride (TiN) and the nitride concentration thereof is between 35 atoms/cm2 and 65 atoms/cm2 inclusive.
    Type: Application
    Filed: February 21, 2012
    Publication date: November 28, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Katsunori Misaki