Patents by Inventor Katsunori Misaki

Katsunori Misaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9595545
    Abstract: A semiconductor device (100) includes: a first line (8) having a first end portion (8T); a second line (2) being insulated from the first line and having a second end portion (2T); a first electrically-conductive portion (9) provided in the neighborhood of the first and second end portions so as to be spaced apart therefrom; a dielectric layer (20) covering them; and a second electrically-conductive portion (38) on the dielectric layer.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: March 14, 2017
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Katsunori Misaki
  • Patent number: 9576696
    Abstract: A drive substrate, including: an insulating substrate (10); an internal connection terminal (12b) made of ITO or IZO provided on the substrate (10); and a lead interconnect (14) that is connected to the connection terminal (12b) with one end thereof lying on the connection terminal and is led out to an outer edge of the insulating substrate (10) at the other end thereof, wherein a contact portion of the lead interconnect (14) with the internal connection terminal (12b) is formed of a barrier metal layer (15A) made of titanium nitride (TiN) and the nitride concentration thereof is between 35 atoms/cm2 and 65 atoms/cm2 inclusive.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: February 21, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Katsunori Misaki
  • Patent number: 9491857
    Abstract: There is provided a wiring connection structure connecting a transparent conductive film formed on a main surface of a transparent substrate having the main surface and a metal wiring formed on the main surface and made of a metal material, wherein the metal wiring is formed to extend from the main surface onto the transparent conductive film and to cover the transparent conductive film.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: November 8, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Katsunori Misaki
  • Patent number: 9383878
    Abstract: An arrangement of a touch panel with improved sensitivity is provided. A touch panel (1) includes: an insulating substrate (10); a first light-shielding portion extending in a first direction; a second light-shielding portion extending in a second direction, the second direction crossing the first direction; a plurality of first insular electrodes (110) arranged in the first direction; a plurality of second insular electrodes (120) arranged in the second direction; a first metal film (141) in contact with the plurality of first insular electrodes (110) and extending in the first direction; a second metal film (152) in contact with the plurality of second insular electrodes (120) and extending in the second direction; and an insulating film (152) provided at least at a crossing of the first metal film (151) and the second metal film (152) as in a plan view for providing electrical insulation between the first metal film (151) and the second metal film (152).
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: July 5, 2016
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Katsunori Misaki
  • Patent number: 9379143
    Abstract: An active matrix substrate (1) includes a source electrode (32), a drain electrode (33), and a semiconductor layer (31) of oxide semiconductor. A gate insulating layer (42) of silicon oxide is formed on the gate electrode (12a); a source electrode (32), a drain electrode (33), and a semiconductor layer (31) are formed on the gate insulating layer (42); a first protection layer (44) of silicon nitride is formed on the gate insulating layer (42) without covering the semiconductor layer (31); and a second protection layer (46) of silicon oxide is formed on the semiconductor layer (31). The first protection layer (44) covers the signal line (14) and the source connection line (36).
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: June 28, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Katsunori Misaki
  • Patent number: 9368523
    Abstract: This semiconductor device (1000A) includes a TFT (100A) with an oxide semiconductor layer 9, a storage capacitor line (12), and a first transparent electrode (15) electrically connected to the storage capacitor line (12). The first transparent electrode (15) includes a portion which overlaps with a first connecting layer (8x) when viewed along a normal to a substrate (1). The portion that overlaps with the first connecting layer (8x) has a point symmetric shape of which a point of symmetry is located inside a contact hole (CH2) when viewed along a normal to the substrate (1). The first transparent electrode (15) is not in direct contact with the first connecting layer (8x). A portion of the first transparent electrode (15) is in direct contact with a second connecting layer (8x). The first connecting layer (8x) is in direct contact with the second connecting layer (19a).
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: June 14, 2016
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Katsunori Misaki, Kunio Matsubara
  • Patent number: 9280013
    Abstract: Provided is a highly reliable configuration of a one glass solution touch panel, in which a sensor electrode and a wiring line can be reliably connected to each other. A touch panel (1) is provided with: an insulating substrate (10) having a sensing area (V) and a non-sensing area (P); sensor electrodes (11, 12), which are formed in the sensing area (P); terminals (13), which are formed in the non-sensing area (P); wiring lines (14), which electrically connect the sensor electrodes (11, 12) and the terminals (13); a light-shielding layer (171), which is formed to cover the non-sensing area (P); and a planarizing film (172), which is formed to cover the light-shielding layer (171). The planarizing film (172) is formed only in the non-sensing area (P).
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: March 8, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Katsunori Misaki
  • Patent number: 9274633
    Abstract: The present invention provides a liquid crystal display device capable of reducing the number of steps and material costs and a method of producing the liquid crystal display device. A liquid crystal display device (100) of the present invention includes a liquid crystal display panel (105); and a touch panel (106). Out of the liquid crystal display panel (105) and the touch panel (106), one panel serves as a reference for alignment between the liquid crystal display panel (105) and the touch panel (106) and the other panel is aligned with the one panel. The other panel is provided with a second alignment mark that is aligned with a first alignment mark of the one panel. The second alignment mark is constituted by a transparent member.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: March 1, 2016
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Katsunori Misaki
  • Patent number: 9246010
    Abstract: In an oxide semiconductor layer, a degree of oxidation S1 of a portion located on the side of the gate insulating film, and a degree of oxidation S2 of surface layer portions located in connection regions with source and drain electrodes have a relation of S2<S1 within a range in which the oxide semiconductor layer has predetermined electric resistance, and a degree of oxidation S3 of a surface layer portion of the channel region is made higher than the degrees of oxidation S1, S2 of the other regions within the range in which the oxide semiconductor layer has the predetermined electric resistance, by annealing the oxide semiconductor layer in an oxygen-containing atmosphere after formation of the source electrode and the drain electrode.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: January 26, 2016
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Katsunori Misaki
  • Publication number: 20150372025
    Abstract: A semiconductor device (100) includes: a first line (8) having a first end portion (8T); a second line (2) being insulated from the first line and having a second end portion (2T); a first electrically-conductive portion (9) provided in the neighborhood of the first and second end portions so as to be spaced apart therefrom; a dielectric layer (20) covering them; and a second electrically-conductive portion (38) on the dielectric layer.
    Type: Application
    Filed: January 23, 2014
    Publication date: December 24, 2015
    Applicant: Sharp Kabushiki Kaisha
    Inventor: Katsunori MISAKI
  • Patent number: 9215800
    Abstract: A external connecting terminal (35) includes a first interconnect layer (36A) formed of a same film as a first conductive pattern for touch position detection under an interlayer insulating film (23), and a second interconnect layer (36B) formed of a same film as a second conductive pattern for touch position detection on the interlayer insulating film (23). the first and the second interconnect layers are electrically connected to a lead line (31) at a portion overlapping the lead line (31), and electrically connected together at a portion outside the lead line (31).
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: December 15, 2015
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Katsunori Misaki
  • Patent number: 9207826
    Abstract: Provided is a touch panel configured to minimize electrode disconnection caused by swelling of the insulating layer during the production process. The touch panel is equipped with: an insulating substrate; first island-shaped electrodes (111) disposed along a first direction; second island-shaped electrodes (121) disposed along a second direction intersecting the first direction; a connecting member (112) for connecting together the first island-shaped electrodes (111); an insulating film (15) formed covering a portion of the connecting member (112); and a relay electrode (122) for connecting together the second island-shaped electrodes (121) over the insulating film (15). The relay electrode (122), in a section thereof that overlaps the connecting member (112) in a plan view, is narrower in width, in a direction perpendicular to the second direction, than the width of the insulating film (15).
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: December 8, 2015
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kunio Matsubara, Katsunori Misaki
  • Patent number: 9182844
    Abstract: A configuration of a touch panel in which an electrode pattern is not readily visible is attained in the present invention. A touch panel is provided with an insulating substrate, first island-shaped electrodes formed on the substrate and arranged in one direction, second island-shaped electrodes formed on the substrate and arranged in a direction intersecting the direction in which the first island-shaped electrodes are arranged, a first connecting member for connecting the first island-shaped electrodes, a metallic film formed on the first connecting member, an insulating film formed so as to completely cover the metallic film, and a second connecting member for connecting the second island-shaped electrodes over the insulating film. The first island-shaped electrodes, the second island-shaped electrodes, the first connecting member, and the second connecting member are formed using a transparent conductive film.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: November 10, 2015
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Katsunori Misaki
  • Publication number: 20150295092
    Abstract: This semiconductor device (201) includes a thin-film transistor (101) having an oxide semiconductor layer (5), wherein each of a source electrode (7) and a drain electrode (9) of the thin-film transistor (101) includes: a main layer (7a, 9a) containing a first metal; a lower layer (7c, 9c) arranged on the substrate side of the main layer, the lower layer (7c, 9c) including, in this order away from the main layer, a lower metal nitride layer made of a nitride of a second metal and a lower metal layer made of the second metal; and an upper layer (7b, 9b) arranged on the opposite side of the main layer from the substrate, the upper layer (7b, 9b) including, in this order away from the main layer, an upper metal nitride layer made of a nitride of the second metal and an upper metal layer made of the second metal, and wherein the first metal is aluminum or copper and the second metal is titanium or molybdenum.
    Type: Application
    Filed: September 19, 2013
    Publication date: October 15, 2015
    Applicant: Sharp Kabushiki Kaisha
    Inventor: Katsunori Misaki
  • Patent number: 9134867
    Abstract: An internal connecting terminal (33) includes a first interconnect layer (34A) formed of a same film as a first conductive pattern for touch position detection under an interlayer insulating film (23), and a second interconnect layer (34B) formed of a same film as a second conductive pattern for touch position detection on the interlayer insulating film (23). The first and the second interconnect layers are electrically connected to a lead line (31) at a portion overlapping the lead line (31), and electrically connected together at a portion outside the lead line (31).
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: September 15, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Katsunori Misaki
  • Publication number: 20150187948
    Abstract: This semiconductor device (100) includes: a gate electrode (12) formed on a substrate (10); a gate insulating layer (20) formed over the gate electrode; an oxide semiconductor layer (18) formed on the gate insulating layer; source and drain electrodes (14, 16) connected to the oxide semiconductor layer; and an insulating layer (22) formed over the source and drain electrodes. The insulating layer includes a silicon nitride layer (22a) which contacts with at least a part of the upper surface of the source and drain electrodes and of which the thickness is greater than 0 nm and equal to or smaller than 30 nm, and a silicon oxide layer (22b) which has been formed on the silicon nitride layer and which has a thickness of more than 30 nm.
    Type: Application
    Filed: July 19, 2013
    Publication date: July 2, 2015
    Inventor: Katsunori Misaki
  • Patent number: 9069219
    Abstract: A source section (S) is made of a source metal (25s) provided above a gate insulating film (23) and an oxide semiconductor film (24a), and a drain section (DR) includes a low resistance portion (24ad) which is part of the oxide semiconductor film (24a), where the part includes a surface of the oxide semiconductor film (24a) opposite to the gate insulating film (23), and the resistance of the part is reduced.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: June 30, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Katsunori Misaki
  • Patent number: 9069221
    Abstract: A liquid crystal display device including a first substrate, with a plurality of bus lines formed thereon such that they intersect with each other, and a second substrate facing the first substrate. The device also includes a plurality of pixel regions defined by the bus lines; a thin film transistor formed in each of the pixel regions; a color filter layer formed in each of the pixel regions; and a pixel electrode formed in each of the pixel regions. A liquid crystal layer is provided between the first substrate and the second substrate. The liquid crystal layer is located next to a polymeric structure formed by irradiating a mixture of liquid crystal materials and ultraviolet-curing monomers with ultraviolet light, and a black display is achieved when no voltage or a subthreshold voltage is applied.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: June 30, 2015
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Manabu Sawasaki, Yuichi Inoue, Masakazu Shibasaki, Naoto Kondo, Tetsuya Fujikawa, Takashi Takagi, Tomonori Tanose, Tomoshige Oda, Akira Komorita, Katsunori Misaki, Shiro Hirota
  • Publication number: 20150177879
    Abstract: A method of manufacturing a touch panel with a reduced number of steps is provided. A method of manufacturing a touch panel (1) includes the steps of; patterning a first transparent conductive film to form a layer containing parts of sensor electrodes (14), (15); patterning a highly-conductive film having a lower electric resistance than the first transparent conductive film to form a layer containing lines (171); patterning a light-shielding film to form a layer containing a light-shielding portion (11); and, after forming the layer containing the light-shielding portion (11), pattering an insulating film to form a layer containing interlayer insulating films (121) and planarizing film (122). The step of patterning a light-shielding film and the step of patterning an insulating film are performed between the step of pattering a first transparent conductive film and the step of patterning a highly-conductive film.
    Type: Application
    Filed: July 26, 2013
    Publication date: June 25, 2015
    Inventor: Katsunori Misaki
  • Publication number: 20150169107
    Abstract: An arrangement of a touch panel is provided that prevents corrosion of the lines and improves reliability. A touch panel includes: a substrate (10); a sensor electrode located on the substrate (10) and formed of an oxide conductive film; a line (161) electrically connected with the sensor electrode; and a protection film (14) provided over the line (161). The protection film (14) includes: a first protection sub-film (141) formed of silicon nitride; a second protection sub-film (142) located on the first protection sub-film (141), formed of silicon nitride and having a lower refractive index than the first protection sub-film (141); and a third protection sub-film (143) located on the second protection sub-film (142), formed of silicon nitride and having a higher refractive index than the second protection sub-film (142), wherein the second protection sub-film (142) has a thickness that is no smaller than the total thickness of the first protection sub-film (141) and the third protection sub-film (143).
    Type: Application
    Filed: June 28, 2013
    Publication date: June 18, 2015
    Inventor: Katsunori Misaki