Patents by Inventor Katsunori Misaki

Katsunori Misaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10811449
    Abstract: Provided is a technique to prevent decreases in the detection accuracy caused by leakage current of photoelectric conversion elements that is caused by permeation of moisture. An active matrix substrate 1 includes a plurality of pixels, each of which includes: a photoelectric conversion element 12 that includes a pair of electrodes 14a, 14b and a semiconductor layer 15 interposed between the electrodes 14a, 14b; an inorganic film 105a that covers a part of a surface of one electrode 14b of the pair of electrodes, and a side surface of the photoelectric conversion element 12; a protection film 105b that has corrosion resistance against moisture, and covers a part of the inorganic film 105a that overlaps with the side surface of the photoelectric conversion element 12; and an organic film 106 that covers the inorganic film 105a and the protection film 105b.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: October 20, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Katsunori Misaki, Kunio Matsubara
  • Patent number: 10811770
    Abstract: A scanning antenna includes a TFT substrate, a slot substrate, and a liquid crystal layer. The TFT substrate includes a transfer terminal section including a patch connection section formed of the same low-resistance metal film as that of a patch electrode, a first protection metal layer formed on the patch connection section, and a first insulating layer including an opening partially exposing an upper face of the first protection metal layer. The slot substrate includes a terminal section including a slot connection section formed of the same low-resistance metal film as that of the slot electrode, a second protection metal layer formed on the slot connection section, and a second insulating layer including an opening partially exposing an upper face of the second protection metal layer.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: October 20, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Katsunori Misaki, Kunio Matsubara
  • Publication number: 20200328236
    Abstract: A scanning antenna provided with an array of a plurality of antenna units includes a transmission and/or reception region including the plurality of antenna units, and a non-transmission and/or reception region other than the transmission and/or reception region. The scanning antenna includes a TFT substrate including a first dielectric substrate, a slot substrate including a second dielectric substrate and a slot electrode supported by a first main surface of the second dielectric substrate, a liquid crystal layer provided between the TFT substrate and the slot substrate, and a reflective conductive plate disposed facing a second main surface of the second dielectric substrate opposite to the first main surface with a dielectric layer interposed between the reflective conductive plate and the second main surface.
    Type: Application
    Filed: April 2, 2020
    Publication date: October 15, 2020
    Inventors: KATSUNORI MISAKI, KUNIO MATSUBARA, YOHJI TANIGUCHI
  • Publication number: 20200328528
    Abstract: A scanning antenna provided with an array of a plurality of antenna units includes a TFT substrate, a slot substrate, and a liquid crystal layer disposed between the TFT substrate and the slot substrate. The slot substrate includes a second dielectric substrate, a slot electrode supported on a first main surface of the second dielectric substrate, and a first dielectric layer disposed between the second dielectric substrate and the slot electrode. The slot electrode has tensile stress. The first dielectric layer has compressive stress.
    Type: Application
    Filed: May 26, 2017
    Publication date: October 15, 2020
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: KATSUNORI MISAKI, SATOSHI UEDA
  • Patent number: 10804314
    Abstract: Provided is an X-ray imaging panel in which off-leakage current can be decreased, and a method for producing the same. An imaging panel includes a photodiode that includes a lower electrode, a photoelectric conversion layer 15 provided on the lower electrode, and an upper electrode 14b provided on the photoelectric conversion layer 15. The photoelectric conversion layer 15 includes a first amorphous semiconductor layer 151, an intrinsic amorphous semiconductor layer 152, and a second amorphous semiconductor layer 153. In the photoelectric conversion layer 15, an upper end portion 1531 of the second amorphous semiconductor layer 153 has a protrusion portion 15a that protrudes toward an outer side of the photoelectric conversion layer 15 with respect to an upper end portion 1521 of the intrinsic amorphous semiconductor layer 152.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: October 13, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Katsunori Misaki
  • Patent number: 10804406
    Abstract: The present invention provides a thin-film transistor substrate including a base substrate and a thin-film transistor, the thin-film transistor including: a gate electrode; a gate insulating layer; a source electrode and a drain electrode; and an oxide semiconductor layer in this order. The source electrode and the drain electrode each include a first conductive layer and a second conductive layer covering the first conductive layer. The second conductive layer contains at least one element selected from the group consisting of molybdenum, tantalum, tungsten, and nickel. The gate insulating layer in a region between the source electrode and the drain electrode has a smaller thickness than in a region below the source electrode and in a region below the drain electrode.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: October 13, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Katsunori Misaki
  • Patent number: 10790319
    Abstract: A TFT substrate includes a gate metal layer including a gate electrode of a TFT and a patch electrode, a gate insulating layer formed on the gate metal layer and including a first opening at least reaching the patch electrode, a source metal layer formed on the gate insulating layer, and including a source electrode of the TFT, a drain electrode, and a drain extending section extending from the drain electrode, an interlayer insulating layer formed on the source metal layer, and including a second opening overlapping the first opening when viewed from a normal direction of a dielectric substrate and a third opening at least reaching the drain extending section, and a conductive layer formed on the interlayer insulating layer and including a patch drain connection section. The patch drain connection section is in contact with the patch electrode within the first opening and in contact with the drain extending section within the third opening.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: September 29, 2020
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Katsunori Misaki
  • Publication number: 20200286935
    Abstract: An imaging panel includes a photoelectric conversion layer. The surface of the photoelectric conversion layer is partly covered with an inorganic insulating film having a first opening above the photoelectric conversion layer. An organic insulating film having a second opening having a larger opening width than the first opening is disposed on the inorganic insulating film. A surface of the inorganic insulating film that is not covered with the organic insulating film is covered with the protection film at the inside of the second opening. The etching rate of the protection film upon etching with an etchant containing an acid is equal to or higher than that of the inorganic insulating film. The surface of the photoelectric conversion layer at the first opening and the surface of the protection film are covered with an electrode.
    Type: Application
    Filed: March 4, 2020
    Publication date: September 10, 2020
    Inventor: Katsunori MISAKI
  • Patent number: 10749257
    Abstract: A TFT substrate includes a dielectric substrate and a plurality of antenna unit regions arranged on the dielectric substrate. Each of the plurality of antenna unit regions includes a TFT and a patch electrode connected to a drain electrode of the TFT. The TFT substrate includes a source metal layer supported by the dielectric substrate and including a source electrode of the TFT, the drain electrode, a source bus line connected to the source electrode, and the patch electrode, a gate metal layer formed on the source metal layer and including a gate electrode of the TFT and a gate bus line connected to the gate electrode, a gate insulating layer formed between the source metal layer and the gate metal layer, and an interlayer insulating layer formed on the gate metal layer.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: August 18, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Katsunori Misaki
  • Patent number: 10749259
    Abstract: This TFT substrate includes a TFT provided with a gate electrode, a source electrode, and a drain electrode; a gate metal layer including the gate electrode; a gate insulating layer formed on the gate metal layer; and a source metal layer that is formed on the gate insulating layer and includes the source electrode, the drain electrode, and a patch electrode. The source metal layer includes a first metal layer that contains one of Ti, Mo, Ta, W and Nb, and a second metal layer that is formed on the first metal layer and contains one of Cu, Al, Ag and Au. The source electrode and the drain electrode each include the first metal layer and the second metal layer. A distance from the first metal layer of the source electrode to the first metal layer of the drain electrode in a channel direction is less than a distance from the second metal layer of the source electrode to the second metal layer of the drain electrode in the channel direction.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: August 18, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Katsunori Misaki
  • Patent number: 10748862
    Abstract: A TFT substrate includes a source-gate connection section in a non-transmission and/or reception region.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: August 18, 2020
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Katsunori Misaki
  • Publication number: 20200259021
    Abstract: A TFT substrate includes a dielectric substrate and a plurality of antenna unit regions arranged on the dielectric substrate. Each of the plurality of antenna unit regions includes a TFT, a patch electrode electrically connected to a drain electrode of the TFT, and a patch drain connection section electrically connecting the drain electrode to the patch electrode, and the patch drain connection section includes a conductive portion included in a conductive layer, the conductive layer being closer to the dielectric substrate than a conductive layer including the patch electrode and being either one of a conductive layer including a gate electrode of the TFT or a conductive layer including a source electrode of TFT, the either one being closer to the dielectric substrate than the other.
    Type: Application
    Filed: May 22, 2018
    Publication date: August 13, 2020
    Inventor: Katsunori MISAKI
  • Patent number: 10707350
    Abstract: A source terminal section of a TFT substrate includes a source terminal lower connection section included in a gate metal layer, and a source terminal upper connection section included in a conductive layer. A source gate connection section includes a source lower connection wiring line included in the gate metal layer and connected to the source terminal lower connection section, a source bus connection section included in a source metal layer and connected to a source bus line, and a source upper connection section included in a conductive layer, and the source upper connection section is in contact with the source lower connection wiring line within a third opening formed in a gate insulating layer and in contact with the source bus connection section within a fifth opening formed in an interlayer insulating layer.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: July 7, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Katsunori Misaki
  • Publication number: 20200176505
    Abstract: An active matrix substrate having a pixel region includes a terminal part, a guard ring, and a connection part that connects the terminal part and the guard ring to each other. The pixel region, the terminal part, and the guard ring each include a first conductive layer in which a first metal film and second metal films that are lower in resistance than the first metal film are stacked, a first protective layer disposed to overlap at least a part of the first conductive layer, and a second protective layer disposed over the first protective layer. The pixel region includes a second conductive layer provided at a higher level than the first protective layer. The connection part includes the first metal film and the second protective layer disposed over the first metal film. Ends of the first conductive layer in the terminal part and the guard ring that face the connection part are located on the inside of ends of the first protective layer that face the connection part.
    Type: Application
    Filed: June 26, 2018
    Publication date: June 4, 2020
    Inventor: Katsunori MISAKI
  • Patent number: 10663823
    Abstract: Provided is a TFT substrate including a dielectric substrate and a plurality of antenna unit regions arranged on the dielectric substrate. The TFT substrate further includes a transmission and/or reception region including the plurality of antenna unit regions, and a non-transmission and/or reception region positioned in a region other than the transmission and/or reception region. Each of the plurality of antenna unit regions is provided with a TFT that is supported by the dielectric substrate and that includes a gate electrode, a semiconductor layer, a gate insulating layer formed between the gate electrode and the semiconductor layer, and a source electrode and a drain electrode-electrically connected to the semiconductor layer; and a patch electrode electrically connected to the drain electrode of the TFT. The patch electrode is formed from the same conductive film as the gate electrode.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: May 26, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Katsunori Misaki
  • Publication number: 20200161367
    Abstract: An imaging panel (1) generates an image based on scintillation light obtained from X-rays transmitted through an object. The imaging panel (1) has an active area and terminal areas on a substrate (100). A protection layer is provided in the active area and the terminal areas, on one of surfaces of the substrate. In the active area (P1), a plurality of elements including switching elements (13) are provided. In the terminal areas (P2, P3), terminal elements (131, 132) connected with any of the plurality of elements are provided. The protection layer includes a barrier layer (101a) in contact with the one surface of the substrate (100), and is provided in a lower layer with respect to the plurality of elements and the terminal elements (131, 132). The barrier layer (101a) contains a material having resistance against an etching material that can etch the substrate (100).
    Type: Application
    Filed: July 10, 2018
    Publication date: May 21, 2020
    Inventors: Katsunori MISAKI, Kunio MATSUBARA
  • Publication number: 20200161360
    Abstract: An active matrix substrate includes a first electrode, a photoelectric conversion element, and a second electrode on a substrate. The first electrode, the photoelectric conversion element, and the second electrode are covered with a first inorganic insulating film including a first opening on the second electrode. The first organic insulating film including a second opening is provided on the first inorganic insulating film, and a surface of the first organic insulating film inside the second opening is covered with a second inorganic insulating film including a third opening overlapping the first opening in a plan view. A conductive film in contact with the second electrode in the first opening is provided on the second inorganic insulating film.
    Type: Application
    Filed: November 12, 2019
    Publication date: May 21, 2020
    Inventor: KATSUNORI MISAKI
  • Publication number: 20200161342
    Abstract: A manufacturing method of a TFT substrate is a manufacturing method of a TFT substrate in which each of a source electrode and a drain electrode includes a lower source metal layer and an upper source metal layer. The manufacturing method of the TFT substrate includes the steps of: forming an upper source metal layer by etching an upper conductive film with the first resist layer as an etching mask; forming a lower source metal layer by etching a lower conductive film; removing the first resist layer and forming a second resist layer covering the upper source metal layer; and forming a source contact portion and a drain contact portion by etching a contact layer by dry etching with the second resist layer as an etching mask.
    Type: Application
    Filed: July 9, 2018
    Publication date: May 21, 2020
    Inventor: Katsunori MISAKI
  • Publication number: 20200135797
    Abstract: An active matrix substrate includes a TFT. The TFT includes a gate electrode, a semiconductor layer overlapping the gate electrode with a gate insulating film interposed therebetween, and a source electrode and a drain electrode disposed on the semiconductor layer. The source electrode, the drain electrode, and the semiconductor layer are covered with a first insulating film. The gate insulating film includes a first stepped portion in a portion covering a peripheral portion of the gate electrode. The first insulating film includes a first opening at a position overlapping a portion of the first stepped portion that is not covered with the source electrode and the drain electrode in a plan view.
    Type: Application
    Filed: October 23, 2019
    Publication date: April 30, 2020
    Inventor: KATSUNORI MISAKI
  • Publication number: 20200136270
    Abstract: A TFT substrate includes a dielectric substrate and a plurality of antenna unit regions arranged on the dielectric substrate, each of the antenna unit regions including a TFT and a patch electrode electrically connected to a drain electrode of the TFT. The TFT substrate includes a gate metal layer supported by the dielectric substrate and including a gate electrode of the TFT, a source metal layer supported by the dielectric substrate and including a source electrode of the TFT, a semiconductor layer, supported by the dielectric substrate, of the TFT, a gate insulating layer formed between the gate metal layer and the semiconductor layer, and a flattened layer formed over the gate insulating layer and formed from an organic insulating material.
    Type: Application
    Filed: June 7, 2018
    Publication date: April 30, 2020
    Inventor: Katsunori MISAKI