Patents by Inventor Katsunori Misaki

Katsunori Misaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200135933
    Abstract: The present invention provides a thin-film transistor substrate including a base substrate and a thin-film transistor, the thin-film transistor including: a gate electrode; a gate insulating layer; a source electrode and a drain electrode; and an oxide semiconductor layer in this order. The source electrode and the drain electrode each include a first conductive layer and a second conductive layer covering the first conductive layer. The second conductive layer contains at least one element selected from the group consisting of molybdenum, tantalum, tungsten, and nickel. The gate insulating layer in a region between the source electrode and the drain electrode has a smaller thickness than in a region below the source electrode and in a region below the drain electrode.
    Type: Application
    Filed: October 24, 2019
    Publication date: April 30, 2020
    Inventor: Katsunori MISAKI
  • Publication number: 20200127055
    Abstract: Provided is an X-ray imaging panel that allows the productivity to be improved and a method for producing the same. An imaging panel 1 generates an image based on scintillation light that is obtained from X-rays transmitted through an object. The imaging panel 1 has an active area and a terminal area on the substrate 101. In the active area, the imaging panel 1 includes a thin film transistor; a first insulating film provided on the thin film transistor; a photoelectric conversion element provided on the first insulating film; a second insulating film separated in a layer above the photoelectric conversion element so as to have a contact hole; and a conductive film that is connected with the photoelectric conversion element through the contact hole. The photoelectric conversion element includes a photoelectric conversion layer that includes a first semiconductor layer, an intrinsic amorphous semiconductor layer, and a second semiconductor layer.
    Type: Application
    Filed: December 22, 2017
    Publication date: April 23, 2020
    Inventor: Katsunori MISAKI
  • Publication number: 20200127012
    Abstract: A TFT substrate includes a dielectric substrate and a plurality of antenna unit regions arranged on the dielectric substrate. Each of the plurality of antenna unit regions includes a TFT and a patch electrode electrically connected to a drain electrode of the TFT. The TFT substrate includes a source metal layer including a source electrode of the TFT, the drain electrode, a source bus line connected to the source electrode, and the patch electrode, a gate metal layer formed on the source metal layer and including a gate electrode of the TFT and a gate bus line connected to the gate electrode, a gate insulating layer formed between the source metal layer and the gate metal layer, and a conductive layer formed on the gate metal layer, and the TFT substrate does not include an insulating layer between the gate metal layer and the conductive layer.
    Type: Application
    Filed: March 30, 2018
    Publication date: April 23, 2020
    Inventor: Katsunori MISAKI
  • Publication number: 20200119445
    Abstract: A TFT substrate includes a transmission and/or reception region including a plurality of antenna unit regions, and a non-transmission and/or reception region located in a region other than the transmission and/or reception region. Each of the plurality of antenna unit regions includes a TFT and a patch electrode electrically connected to a drain electrode of the TFT. The TFT substrate includes a source metal layer including: a source electrode of the TFT, the drain electrode, and a source bus line; a gate metal layer formed on the source metal layer and including a gate electrode of the TFT, a gate bus line, and a patch electrode; a gate insulating layer formed between the source metal layer and the gate metal layer; and a conductive layer formed on the gate metal layer, and the TFT substrate does not include an insulating layer between the gate metal layer and the conductive layer.
    Type: Application
    Filed: March 30, 2018
    Publication date: April 16, 2020
    Inventor: Katsunori MISAKI
  • Publication number: 20200112106
    Abstract: The TFT substrate includes a dielectric substrate and a plurality of antenna unit regions arranged on the dielectric substrate. Each of the plurality of antenna unit regions includes a TFT, an patch electrode electrically connected to a drain electrode of the TFT, an auxiliary capacitance electrode electrically connected to the drain electrode, a first auxiliary capacitance counter electrode opposite to the auxiliary capacitance electrode with a dielectric layer interposed therebetween, and a second auxiliary capacitance counter electrode on a side of the auxiliary capacitance electrode farther from the first auxiliary capacitance counter electrode and opposite to the auxiliary capacitance electrode with another dielectric layer interposed therebetween.
    Type: Application
    Filed: March 29, 2018
    Publication date: April 9, 2020
    Inventor: Katsunori MISAKI
  • Publication number: 20200099124
    Abstract: The scanning antenna includes a TFT substrate, a slot substrate including a slot electrode, a liquid crystal layer provided between the TFT substrate and the slot substrate, and a reflective conductive plate. Each of the plurality of antenna units includes a TFT, a patch electrode electrically connected to the drain of the TFT, a slot formed in the slot electrode corresponding to the patch electrode, and a first region in which the patch electrode and the slot electrode overlap each other when viewed from the normal direction of the first dielectric substrate. A distrance in the normal direction of the first dielectric substrate between the patch electrode and the slot electrode of the plurality of second antenna units is smaller than a distance in the normal direction of the first dielectric substrate between the patch electrode and the slot electrode of the plurality of first antenna units.
    Type: Application
    Filed: September 25, 2019
    Publication date: March 26, 2020
    Inventors: KUNIO MATSUBARA, KATSUNORI MISAKI
  • Publication number: 20200091220
    Abstract: An active matrix substrate includes a photoelectric conversion element, an electrode provided on at least one main surface of the photoelectric conversion element, and a first inorganic film covering a side surface of the photoelectric conversion element. The electrode includes an extending section covering the side surface of the photoelectric conversion element through intermediation of the first inorganic film.
    Type: Application
    Filed: September 12, 2019
    Publication date: March 19, 2020
    Inventor: KATSUNORI MISAKI
  • Publication number: 20200083604
    Abstract: A TFT substrate includes a dielectric substrate and a plurality of antenna unit regions arranged on the dielectric substrate. Each of the plurality of antenna unit regions includes a TFT and a patch electrode connected to a drain electrode of the TFT. The TFT substrate includes a source metal layer supported by the dielectric substrate and including a source electrode of the TFT, the drain electrode, a source bus line connected to the source electrode, and the patch electrode, a gate metal layer formed on the source metal layer and including a gate electrode of the TFT and a gate bus line connected to the gate electrode, a gate insulating layer formed between the source metal layer and the gate metal layer, and an interlayer insulating layer formed on the gate metal layer.
    Type: Application
    Filed: December 5, 2017
    Publication date: March 12, 2020
    Inventor: Katsunori MISAKI
  • Patent number: 10580818
    Abstract: Provided is an X-ray imaging panel and a method for producing the same with improved productivity. An imaging panel 1 has an active area and a terminal area on a substrate 101. In the terminal area, there are provided: a first conductive layer 100; a terminal first insulating film 103 that is formed with the same material as that of a first insulating film in the active area, and has a first opening; a second conductive layer 1701 that is formed with the same material as that of a conductive film in the active area, and overlaps with the first conductive layer 100 at a position where the first opening is provided; and a cover layer provided at the position where the first opening is provided, so as to be arranged between the first conductive layer 100 and the second conductive layer 1701. The first conductive layer 100 is formed with the same material as that of any one of a gate electrode and a source electrode of a thin film transistor as well as a lower electrode in the active area.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: March 3, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Katsunori Misaki
  • Patent number: 10573641
    Abstract: A TFT substrate includes a TFT, a patch electrode electrically connected to the TFT, a gate metal layer, a gate insulating layer, a source metal layer, a first insulating layer, and a patch metal layer including the patch electrode. The gate metal layer includes a plurality of gate connection wiring lines disposed in a non-transmission and/or reception region. The source bus lines SL are each electrically connected to one of the gate connection wiring lines via a conductor section. The conductor section is in contact with the gate connection wiring line in a second opening provided in the gate insulating layer and the first insulating layer and with the source bus line SL in a first opening provided in the first insulating layer. The patch metal layer further includes a first patch connection section located in the first opening and/or the second opening. The first patch connection section includes the conductor section or is disposed on the conductor section.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: February 25, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Katsunori Misaki
  • Publication number: 20200043973
    Abstract: An imaging panel includes a photoelectric conversion layer on a side of one of surfaces of a substrate. Further, the imaging panel includes an electrode connected to one of surfaces of the photoelectric conversion layer, a bias line connected with the electrode, and a protection film that is made of a material resistant against an etching agent containing hydrofluoric acid, and covers side surfaces of the bias line.
    Type: Application
    Filed: August 1, 2019
    Publication date: February 6, 2020
    Inventor: KATSUNORI MISAKI
  • Publication number: 20200014120
    Abstract: A TFT substrate includes a dielectric substrate, a plurality of antenna unit regions arranged on the dielectric substrate, each antenna unit region including a TFT, a patch electrode electrically connected to a drain electrode of the TFT, an auxiliary capacitance electrode electrically connected to the drain electrode, and auxiliary capacitance counter electrodes opposite the auxiliary capacitance electrode with an insulating layer interposed therebetween, and a plurality of CS bus lines, each CS bus line being connected to any of the auxiliary capacitance counter electrodes. Each of the plurality of CS bus lines includes at least two conductive layers disposed with an insulating layer disposed therebetween.
    Type: Application
    Filed: February 27, 2018
    Publication date: January 9, 2020
    Inventor: Katsunori MISAKI
  • Publication number: 20190385960
    Abstract: A TFT substrate includes a source-gate connection section in a non-transmission and/or reception region.
    Type: Application
    Filed: December 1, 2017
    Publication date: December 19, 2019
    Applicant: Sharp Kabushiki Kaisha
    Inventor: Katsunori MISAKI
  • Publication number: 20190355774
    Abstract: Provided is an X-ray imaging panel and a method for producing the same with improved productivity. An imaging panel 1 has an active area and a terminal area on a substrate 101. In the terminal area, there are provided: a first conductive layer 100; a terminal first insulating film 103 that is formed with the same material as that of a first insulating film in the active area, and has a first opening; a second conductive layer 1701 that is formed with the same material as that of a conductive film in the active area, and overlaps with the first conductive layer 100 at a position where the first opening is provided; and a cover layer provided at the position where the first opening is provided, so as to be arranged between the first conductive layer 100 and the second conductive layer 1701. The first conductive layer 100 is formed with the same material as that of any one of a gate electrode and a source electrode of a thin film transistor as well as a lower electrode in the active area.
    Type: Application
    Filed: February 7, 2018
    Publication date: November 21, 2019
    Inventor: Katsunori MISAKI
  • Publication number: 20190341691
    Abstract: A TFT substrate includes a transmission and/or reception region including a plurality of antenna unit regions, and a non-transmission and/or reception region located in a region other than the transmission and/or reception region. Each of the plurality of antenna unit regions includes a TFT and a patch electrode electrically connected to a drain electrode of the TFT. The TFT substrate includes a source metal layer including a source electrode of the TFT, the drain electrode, and a source bus line, a gate metal layer formed on the source metal layer and including a gate electrode of the TFT and a gate bus line, a gate insulating layer formed between the source metal layer and the gate metal layer, an interlayer insulating layer formed on the gate metal layer, and a conductive layer formed on the interlayer insulating layer. The patch electrode is included in the gate metal layer.
    Type: Application
    Filed: December 18, 2017
    Publication date: November 7, 2019
    Inventor: Katsunori MISAKI
  • Publication number: 20190335116
    Abstract: Provided is an X-ray imaging panel in which leakage current can be reduced, and a method for producing the same. An imaging panel 1 generates an image based on scintillation light that is obtained from X-rays transmitted through an object. The imaging panel 1 includes a photoelectric conversion layer 15 that converts scintillation light into charges, on a substrate. The photoelectric conversion layer 15 has a polygonal shape having a plurality of corner portions 15p when viewed in a plan view.
    Type: Application
    Filed: December 22, 2017
    Publication date: October 31, 2019
    Inventor: Katsunori MISAKI
  • Publication number: 20190296065
    Abstract: Provided is a technique to prevent decreases in the detection accuracy caused by leakage current of photoelectric conversion elements that is caused by permeation of moisture. An active matrix substrate 1 includes a plurality of pixels, each of which includes: a photoelectric conversion element 12 that includes a pair of electrodes 14a, 14b and a semiconductor layer 15 interposed between the electrodes 14a, 14b; an inorganic film 105a that covers a part of a surface of one electrode 14b of the pair of electrodes, and a side surface of the photoelectric conversion element 12; a protection film 105b that has corrosion resistance against moisture, and covers a part of the inorganic film 105a that overlaps with the side surface of the photoelectric conversion element 12; and an organic film 106 that covers the inorganic film 105a and the protection film 105b.
    Type: Application
    Filed: March 25, 2019
    Publication date: September 26, 2019
    Inventors: Katsunori MISAKI, Kunio MATSUBARA
  • Publication number: 20190296076
    Abstract: Provided is an X-ray imaging panel in which leakage current in a photoelectric conversion layer can be decreased, and a method for producing the same. An imaging panel 1 generates an image based on scintillation light that is obtained from X-rays transmitted through an object. The imaging panel 1 includes a thin film transistor 13 on a substrate 101; an insulating film 103 that covers the thin film transistor 13; a photoelectric conversion layer 15 that converts scintillation light into charges; an upper electrode 14b; a lower electrode 14a that is connected with the thin film transistor 13; and a protection film 142 that covers a side end portion of the lower electrode 14a.
    Type: Application
    Filed: October 6, 2017
    Publication date: September 26, 2019
    Inventor: Katsunori MISAKI
  • Publication number: 20190296057
    Abstract: A TFT substrate includes a gate metal layer including a gate electrode of a TFT and a patch electrode, a gate insulating layer formed on the gate metal layer and including a first opening at least reaching the patch electrode, a source metal layer formed on the gate insulating layer, and including a source electrode of the TFT, a drain electrode, and a drain extending section extending from the drain electrode, an interlayer insulating layer formed on the source metal layer, and including a second opening overlapping the first opening when viewed from a normal direction of a dielectric substrate and a third opening at least reaching the drain extending section, and a conductive layer formed on the interlayer insulating layer and including a patch drain connection section. The patch drain connection section is in contact with the patch electrode within the first opening and in contact with the drain extending section within the third opening.
    Type: Application
    Filed: October 17, 2017
    Publication date: September 26, 2019
    Applicant: Sharp Kabushiki Kaisha
    Inventor: Katsunori MISAKI
  • Publication number: 20190296444
    Abstract: A TFT substrate includes a TFT, a patch electrode electrically connected to the TFT, a gate metal layer, a gate insulating layer, a source metal layer, a first insulating layer, and a patch metal layer including the patch electrode. The gate metal layer includes a plurality of gate connection wiring lines disposed in a non-transmission and/or reception region. The source bus lines SL are each electrically connected to one of the gate connection wiring lines via a conductor section. The conductor section is in contact with the gate connection wiring line in a second opening provided in the gate insulating layer and the first insulating layer and with the source bus line SL in a first opening provided in the first insulating layer. The patch metal layer further includes a first patch connection section located in the first opening and/or the second opening. The first patch connection section includes the conductor section or is disposed on the conductor section.
    Type: Application
    Filed: May 8, 2017
    Publication date: September 26, 2019
    Inventor: KATSUNORI MISAKI