Patents by Inventor Katsuyuki Sekine

Katsuyuki Sekine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150263034
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body having a plurality of electrode layers containing boron and silicon, and a plurality of insulating layers each provided between the electrode layers; a channel body penetrating through the stacked body; and a memory film provided between the channel body and each of the electrode layer. The memory film includes a tunnel film, a charge storage film, and a block film, provided in order from the channel body side. The block film includes a silicon nitride film, and a first silicon oxide film provided between the silicon nitride film and the electrode layer and being in contact with the electrode layer.
    Type: Application
    Filed: September 10, 2014
    Publication date: September 17, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaaki HIGUCHI, Hirokazu ISHIGAKI, Masao SHINGU, Katsuyuki SEKINE
  • Publication number: 20150263126
    Abstract: According to one embodiment, a plurality of electrode films, a semiconductor pillar, a tunnel insulating film, a charge storage film, and a block insulating film. The plurality of electrode films are arranged to be separated each other along a first direction. The block insulating film includes a silicon oxide layer, and a high dielectric constant layer made of high dielectric constant material having a dielectric constant higher than a dielectric constant of silicon oxide. The high dielectric constant layer has a first portion and a second portion. The first portion is disposed between the semiconductor pillar and a space between the electrode films. The second portion is disposed between the semiconductor pillar and the electrode films. In a direction perpendicular to the first direction, a thickness of the first portion is thinner than a thickness of the second portion.
    Type: Application
    Filed: March 11, 2015
    Publication date: September 17, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masao SHINGU, Katsuyuki Sekine
  • Patent number: 9105738
    Abstract: A semiconductor device includes a multilayered interelectrode insulating film formed between a charge storage layer and a control electrode layer. The interelectrode insulating film is formed in a first region above an upper surface portion of the element isolation insulating film, a second region along a sidewall portion of the charge storage layer, and a third region above an upper surface portion of the charge storage layer. The interelectrode insulating film includes a stack of first silicon oxide film, a silicon nitride film, and a second silicon oxide film. The silicon nitride film is relatively thicker in the third region compared to the first region and compared to at least a portion of the second region.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 11, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Katsuyuki Sekine
  • Publication number: 20150171318
    Abstract: A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer
    Type: Application
    Filed: December 12, 2014
    Publication date: June 18, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Takano, Yoshio Ozawa, Katsuyuki Sekine, Junichi Wada
  • Patent number: 8941088
    Abstract: A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: January 27, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Takano, Yoshio Ozawa, Katsuyuki Sekine, Junichi Wada
  • Patent number: 8866117
    Abstract: A diode layer includes a first impurity semiconductor layer that includes a first impurity acting as an acceptor and a second impurity semiconductor layer that includes a second impurity acting as a donor. One end of a first electrode layer contacts the diode layer. One end of a polysilicon layer contacts the other end of the first electrode layer. One end of a variable resistance layer contacts the other end of the polysilicon layer and is able to change a resistance value. A second electrode layer contacts the other end of the variable resistance layer. At least one of a first area and a second area contains a third impurity. The first area includes one end of the polysilicon layer, the second area includes the other end of the polysilicon layer. The third impurity differs from the first impurity and the second impurity.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: October 21, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Sekine, Yasuhiro Nojiri, Hiroyuki Fukumizu
  • Patent number: 8837225
    Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate and memory transistors, each of which has a laminate formed by alternately laminating insulating films and conductive films on the semiconductor substrate, a silicon pillar going through the laminate, a tunnel insulating film arranged on the surface of the silicon pillar facing the laminate, a charge accumulating layer arranged on the surface of the tunnel insulating film facing the laminate, and a block insulating film arranged on the surface of the charge accumulating layer facing the laminate and in contact with the conductive film. During a data deletion operation, a voltage is applied on the conductive film so that the potential of the silicon pillar with respect to the conductive film decreases as the cross-sectional area of the silicon pillar decreases.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaaki Higuchi, Katsuyuki Sekine, Ryota Katsumata, Hiroaki Hazama
  • Publication number: 20140252453
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device including a semiconductor layer with a main surface, a first insulating layer formed on the main surface of the semiconductor layer, a charge storage layer formed on the first insulating layer, a second insulating layer formed on the charge storage layer, and a control gate electrode formed on the second insulating layer. At least one inelastic scattering film that reduces energy of electrons by scattering is contained in at least one of the charge storage layer and second insulating layer.
    Type: Application
    Filed: May 22, 2014
    Publication date: September 11, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaaki HIGUCHI, Yoshio Ozawa, Katsuyuki Sekine, Ryota Fujitsuka
  • Patent number: 8829593
    Abstract: A first select transistor is formed on a semiconductor substrate. Memory cell transistors are stacked on the first select transistor and connected in series. A second select transistor is formed on the memory cell transistors. The memory cell transistors include a tapered semiconductor pillar which increases in diameter from the first select transistor toward the second select transistor, a tunnel dielectric film formed on the side surface of the semiconductor pillar, a charge storage layer which is formed on the side surface of the tunnel dielectric film and which increases in charge trap density from the first select transistor side toward the second select transistor side, a block dielectric film formed on the side surface of the charge storage layer, and conductor films which are formed on the side surface of the block dielectric film and which serve as gate electrodes.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: September 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Sekine, Kensuke Takano, Masaaki Higuchi, Tetsuya Kai, Yoshio Ozawa
  • Patent number: 8759901
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device including a semiconductor layer with a main surface, a first insulating layer formed on the main surface of the semiconductor layer, a charge storage layer formed on the first insulating layer, a second insulating layer formed on the charge storage layer, and a control gate electrode formed on the second insulating layer. At least one inelastic scattering film that reduces energy of electrons by scattering is contained in at least one of the charge storage layer and second insulating layer.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaaki Higuchi, Yoshio Ozawa, Katsuyuki Sekine, Ryota Fujitsuka
  • Patent number: 8759806
    Abstract: A semiconductor memory device in an embodiment comprises memory cells, each of the memory cells disposed between a first line and a second line and having a variable resistance element and a switching element connected in series. The variable resistance element includes a variable resistance layer configured to change in resistance value thereof between a low-resistance state and a high-resistance state. The variable resistance layer is configured by a transition metal oxide. A ratio of transition metal and oxygen configuring the transition metal oxide varies between 1:1 and 1:2 along a first direction directed from the first line to the second line.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Yamaguchi, Hirofumi Inoue, Reika Ichihara, Takayuki Tsukamoto, Takashi Shigeoka, Katsuyuki Sekine, Shinya Aoki
  • Publication number: 20140021430
    Abstract: A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer
    Type: Application
    Filed: September 27, 2013
    Publication date: January 23, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Takano, Yoshio Ozawa, Katsuyuki Sekine, Junichi Wada
  • Publication number: 20140010016
    Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate and memory transistors, each of which has a laminate formed by alternately laminating insulating films and conductive films on the semiconductor substrate, a silicon pillar going through the laminate, a tunnel insulating film arranged on the surface of the silicon pillar facing the laminate, a charge accumulating layer arranged on the surface of the tunnel insulating film facing the laminate, and a block insulating film arranged on the surface of the charge accumulating layer facing the laminate and in contact with the conductive film. During a data deletion operation, a voltage is applied on the conductive film so that the potential of the silicon pillar with respect to the conductive film decreases as the cross-sectional area of the silicon pillar decreases.
    Type: Application
    Filed: March 6, 2013
    Publication date: January 9, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaaki HIGUCHI, Katsuyuki SEKINE, Ryota KATSUMATA, Hiroaki HAZAMA
  • Patent number: 8609487
    Abstract: A method of manufacturing a semiconductor device comprising a first insulating film formed on a semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, wherein forming the second insulating film comprises forming an insulating film containing silicon using source gas not containing chlorine, and forming an insulating film containing oxygen and a metal element on the insulating film containing silicon.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: December 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuaki Natori, Masayuki Tanaka, Akihito Yamamoto, Katsuyuki Sekine, Ryota Fujitsuka, Daisuke Nishida, Yoshio Ozawa
  • Patent number: 8604536
    Abstract: A semiconductor device includes a memory cell transistor including a first lower insulating film provided on a semiconductor substrate, a first intermediate insulating film provided on the first lower insulating film, a first upper insulating film provided on the first intermediate insulating film, and a first gate electrode provided on the first upper insulating film, and a select transistor including a second lower insulating film provided on the semiconductor substrate, a second intermediate insulating film provided on the second lower insulating film, a second upper insulating film provided on the second intermediate insulating film, and a second gate electrode provided on the second upper insulating film, wherein trap density of the second intermediate insulating film is lower than that of the first intermediate insulating film.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: December 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Sekine, Yoshio Ozawa
  • Patent number: 8598561
    Abstract: A nonvolatile memory device includes first and second conductive layers, a resistance change layer, and a rectifying element. The first conductive layer has first and second major surfaces. The second conductive layer has third and fourth major surfaces, a side face, and a corner part. The third major surface faces the first major surface and includes a plane parallel to the first major surface and is provided between the fourth and first major surfaces. The corner part is provided between the third major surface and the side face and has a curvature higher than that of the third major surface. The resistance change layer is provided between the first and second conductive layers. The rectifying element faces the second major surface of the first conductive layer. An area of the third major surface is smaller than that of the second major surface.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: December 3, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Sekine, Ryota Fujitsuka, Yoshio Ozawa
  • Patent number: 8569728
    Abstract: A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: October 29, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Takano, Yoshio Ozawa, Katsuyuki Sekine, Junichi Wada
  • Patent number: 8558208
    Abstract: According to one embodiment, there are provided a first electrode, a second electrode, first and second variable-resistance layers that are arranged between the first electrode and the second electrode, and at least one non variable-resistance layer that is arranged so that positions of the first and second variable-resistance layers between the first electrode and the second electrode are symmetrical to each other.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: October 15, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryota Fujitsuka, Masahiro Kiyotoshi, Katsuyuki Sekine, Mitsuru Sato
  • Publication number: 20130240968
    Abstract: A semiconductor device includes a multilayered interelectrode insulating film formed between a charge storage layer and a control electrode layer. The interelectrode insulating film is formed in a first region above an upper surface portion of the element isolation insulating film, a second region along a sidewall portion of the charge storage layer, and a third region above an upper surface portion of the charge storage layer. The interelectrode insulating film includes a stack of first silicon oxide film, a silicon nitride film, and a second silicon oxide film. The silicon nitride film is relatively thicker in the third region compared to the first region and compared to at least a portion of the second region.
    Type: Application
    Filed: September 14, 2012
    Publication date: September 19, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Katsuyuki SEKINE
  • Publication number: 20130234096
    Abstract: A diode layer includes a first impurity semiconductor layer that includes a first impurity acting as an acceptor and a second impurity semiconductor layer that includes a second impurity acting as a donor. One end of a first electrode layer contacts the diode layer. One end of a polysilicon layer contacts the other end of the first electrode layer. One end of a variable resistance layer contacts the other end of the polysilicon layer and is able to change a resistance value. A second electrode layer contacts the other end of the variable resistance layer. At least one of a first area and a second area contains a third impurity. The first area includes one end of the polysilicon layer, the second area includes the other end of the polysilicon layer. The third impurity differs from the first impurity and the second impurity.
    Type: Application
    Filed: August 31, 2012
    Publication date: September 12, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsuyuki SEKINE, Yasuhiro Nojiri, Hiroyuki Fukumizu