Patents by Inventor Katsuyuki Sekine

Katsuyuki Sekine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120012807
    Abstract: A semiconductor memory device in an embodiment comprises memory cells, each of the memory cells disposed between a first line and a second line and having a variable resistance element and a switching element connected in series. The variable resistance element includes a variable resistance layer configured to change in resistance value thereof between a low-resistance state and a high-resistance state. The variable resistance layer is configured by a transition metal oxide. A ratio of transition metal and oxygen configuring the transition metal oxide varies between 1:1 and 1:2 along a first direction directed from the first line to the second line.
    Type: Application
    Filed: July 13, 2011
    Publication date: January 19, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takeshi YAMAGUCHI, Hirofumi Inoue, Reika Ichihara, Takayuki Tsukamoto, Takashi Shigeoka, Katsuyuki Sekine, Shinya Aoki
  • Patent number: 8089121
    Abstract: A nonvolatile semiconductor memory device includes a semiconductor layer as a channel, a conductive layer which is formed on a surface of the semiconductor layer with a first insulating layer and a second insulating layer interposed therebetween and functions as a control gate electrode; and a plurality of first charge storage layers formed between the first insulating layer and the second insulating layer. The plurality of first charge storage layers are formed in isolation from one another along a surface of the first insulating layer. The first insulating layer is formed so as to protrude towards the semiconductor layer at a position where each of the first charge storage layers is formed.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: January 3, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Takano, Yoshio Ozawa, Katsuyuki Sekine, Masaru Kito
  • Patent number: 8080463
    Abstract: A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: December 20, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuaki Iwasawa, Takeshi Hoshi, Keisuke Nakazawa, Shogo Matsuo, Takashi Nakao, Ryu Kato, Tetsuya Kai, Katsuyuki Sekine
  • Patent number: 8022486
    Abstract: A semiconductor device includes a semiconductor substrate, and a p-channel MOS transistor provided on the semiconductor substrate, the p-channel MOS transistor comprising a first gate dielectric film including Hf, a second gate dielectric film provided on the first gate dielectric film and including aluminum oxide, and a first metal silicide gate electrode provided on the second gate dielectric film.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: September 20, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Sekine, Tomonori Aoyama, Takuya Kobayashi
  • Patent number: 8008152
    Abstract: A method of manufacturing a semiconductor device comprising a first insulating film formed on a semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, forming the second insulating film comprises forming a lower insulating film containing oxygen and a metal element, thermally treating the lower insulating film in an atmosphere containing oxidizing gas, and forming an upper insulating film on the thermally treated lower insulating film using film forming gas containing at least one of hydrogen and chlorine.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: August 30, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryota Fujitsuka, Katsuaki Natori, Daisuke Nishida, Masayuki Tanaka, Katsuyuki Sekine, Yoshio Ozawa, Akihito Yamamoto
  • Patent number: 7999304
    Abstract: A semiconductor device includes a semiconductor substrate, and nonvolatile memory cells, each of the cells including a channel region having a channel length and a channel width, a tunnel insulating film, a floating gate electrode, a control gate electrode, an inter-electrode insulating film between the floating and control gate electrodes, and an electrode side-wall insulating film on side-wall surfaces of the floating and control gate electrodes, the electrode side-wall insulating film including first and second insulating films having first and second dielectric constants, the first dielectric constant being higher than the second dielectric constant, the second dielectric constant being higher than a dielectric constant of a silicon nitride film, the first insulating film being in a central region of a facing region between the floating and control gate electrodes, the second insulating region being in the both end regions of the facing region and protruding from the both end portions.
    Type: Grant
    Filed: February 6, 2008
    Date of Patent: August 16, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Ozawa, Akihito Yamamoto, Katsuaki Natori, Masayuki Tanaka, Katsuyuki Sekine, Daisuke Nishida, Ryota Fujitsuka
  • Publication number: 20110193050
    Abstract: According to one embodiment, a semiconductor memory device comprises a substrate, a lower electrode, a variable resistance film, and an upper electrode. The lower electrode is on the substrate. The variable resistance film is on the lower electrode and stores data. The upper electrode is on the variable resistance film. The variable resistance film comprises a first film, and a second film. The first film is on a side of at least one of the upper electrode and the lower electrode and contains a metal. The second film is between the first film and the other electrode and contains the metal and oxygen. A composition ratio [O]/[Me] of oxygen to the metal in the second film is lower than a stoichiometric ratio and higher than the composition ratio [O]/[Me] in the first film. The composition ratio [0]/[Me] changes between the first film and the second film.
    Type: Application
    Filed: September 17, 2010
    Publication date: August 11, 2011
    Inventors: Kensuke Takano, Katsuyuki Sekine, Yoshio Ozawa
  • Publication number: 20110175048
    Abstract: According to one embodiment, a nonvolatile memory device includes first and second conductive layers, a resistance change layer, and a rectifying element. The first conductive layer has first and second major surfaces. The second conductive layer has third and fourth major surfaces, a side face, and a corner part. The third major surface faces the first major surface and includes a plane parallel to the first major face and is provided between the fourth and first major surfaces. The corner part is provided between the third major surface and the side face. The corner part has a curvature higher than that of the third major surface. The resistance change layer is provided between the first and second conductive layers. The rectifying element faces the second major surface of the first conductive layer. An area of the third major surface is smaller than that the second major surface.
    Type: Application
    Filed: January 11, 2011
    Publication date: July 21, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsuyuki SEKINE, Ryota FUJITSUKA, Yoshio OZAWA
  • Publication number: 20110176351
    Abstract: According to one embodiment, a nonvolatile memory device includes a memory layer and a control unit. The memory layer includes a first conductive layer, a second conductive layer and a resistance change layer. The resistance change layer is provided between the first and second conductive layers and transits between a high resistance state and a low resistance state by at least one of an applied electric field and an applied current. The control unit is electrically connected to the first and second conductive layers and configured to apply a first signal with a first polarity between the first and second conductive layers prior to applying a second signal with a second polarity different from the first polarity between the first and second conductive layers to cause the resistance change layer to transit from the high resistance state to the low resistance state.
    Type: Application
    Filed: June 28, 2010
    Publication date: July 21, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryota FUJITSUKA, Katsuyuki Sekine, Yoshio Ozawa
  • Publication number: 20110175157
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor layer; first and second insulating layers; a functional layer; first and second gate electrodes. The first insulating layer opposes the semiconductor layer. The second insulating layer is provided between the semiconductor layer and the first insulating layer. The functional layer is provided between the first and second insulating layers. The second gate electrode is separated from the first gate electrode. The first insulating layer is disposed between the first gate electrode and the semiconductor layer and between the second gate electrode and the semiconductor layer. The charge storabilities in first and second regions of the functional layer are different from that of a third region of the functional layer. The first and second regions oppose the first and second gate electrodes, respectively. The third region is between the first and the second regions.
    Type: Application
    Filed: January 18, 2011
    Publication date: July 21, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki SEKINE, Tetsuya Kai, Yoshio Ozawa
  • Patent number: 7972927
    Abstract: According to a method of manufacturing a MONOS nonvolatile semiconductor memory device, a tunnel insulating film, a charge storage layer, a block insulating film containing a metal oxide and a control gate electrode are stacked on a semiconductor substrate. Heat treatment is carried out in an atmosphere containing an oxidizing gas after the tunnel insulating film, the charge storage layer and the block insulating film are stacked on the semiconductor substrate. Thereafter, the control gate electrode is formed on the block insulating film.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: July 5, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryota Fujitsuka, Katsuyuki Sekine, Yoshio Ozawa
  • Patent number: 7968397
    Abstract: A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO2, or a mixture of a tetravalent metal oxide and SiON and which containing B when it is in an nMOS structure on the semiconductor substrate or containing at least one of P and As when it is in a pMOS structure on the semiconductor substrate, and a gate electrode made of a metal having a work function of 4 eV to 5.5 eV.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: June 28, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akio Kaneko, Seiji Inumiya, Katsuyuki Sekine, Kazuhiro Eguchi, Motoyuki Sato
  • Patent number: 7964489
    Abstract: A semiconductor device includes: a p-channel MIS transistor including: a first insulating layer formed on a semiconductor region between a source region and a drain region, and containing at least silicon and oxygen; a second insulating layer formed on the first insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, and a first gate electrode formed on the second insulating layer. The first and second insulating layers have a first and second region respectively. The first and second regions are in a 0.3 nm range in the film thickness direction from an interface between the first insulating layer and the second insulating layer. Each of the first and second regions include aluminum atoms with a concentration of 1×1020 cm?3 or more to 1×1022 cm?3 or less.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: June 21, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masato Koyama, Yoshinori Tsuchiya, Yuuichi Kamimuta, Reika Ichihara, Katsuyuki Sekine
  • Publication number: 20110140068
    Abstract: According to one embodiment, a resistance-change memory cell array in which a plurality of horizontal electrodes extending horizontally and a plurality of vertical electrodes extending vertically are arranged to configure a cross-point structure includes rectifying insulating films formed in contact with side surfaces of the vertical electrodes in facing regions between the horizontal electrodes and the vertical electrodes, variable resistance films formed in contact with side surfaces of the horizontal electrodes in the facing regions between the horizontal electrodes and the vertical electrodes, and conductive layers formed between the rectifying insulating films and the variable resitstance films.
    Type: Application
    Filed: November 8, 2010
    Publication date: June 16, 2011
    Inventors: Yoshio OZAWA, Katsuyuki Sekine
  • Patent number: 7928500
    Abstract: A semiconductor device includes a tunnel insulating film formed on a semiconductor substrate, a floating gate electrode formed on the tunnel insulating film, an inter-electrode insulating film formed on the floating gate electrode, and a control gate electrode formed on the inter-electrode insulating film, wherein the inter-electrode insulating film includes a main insulating film and a plurality of nano-particles in the main insulating film.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: April 19, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Sekine, Yoshio Ozawa, Hiroaki Tsunoda
  • Patent number: 7927949
    Abstract: A semiconductor memory device manufacturing method includes forming a floating gate electrode above a semiconductor substrate, forming an interelectrode insulating film above the floating gate electrode, forming a first radical nitride film on a surface of the interelectrode insulating film by first radical nitriding, and forming a control gate electrode on the first radical nitride film.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: April 19, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Ozawa, Isao Kamioka, Junichi Shiozawa, Akihito Yamamoto, Ryota Fujitsuka, Yoshihiro Ogawa, Katsuaki Natori, Katsuyuki Sekine, Masayuki Tanaka, Daisuke Nishida
  • Publication number: 20110068312
    Abstract: According to one embodiment, a nonvolatile memory device comprises a plurality of first lines, a plurality of second lines, and memory cells. Each of the memory cells comprise a variable resistor, and a diode. The variable resistor includes a first metal oxide film and is configured to reversibly change resistance value by energy application. The diode includes a second metal oxide film and is connected in series to the variable resistor. The first metal oxide film has at least one of dielectric constant lower than that of the second metal oxide film and physical film thickness greater than that of the second metal oxide film.
    Type: Application
    Filed: June 7, 2010
    Publication date: March 24, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsuyuki SEKINE, Yoshio Ozawa
  • Publication number: 20110068316
    Abstract: According to one embodiment, a nonvolatile memory device includes a plurality of nonvolatile memory elements each of that includes a resistance change film. The resistance change film is capable of recording information by transitioning between a plurality of states having different resistances in response to at least one of a voltage applied to the resistance change film or a current passed through the resistance change film, and the resistance change film includes an oxide containing at least one element selected from the group consisting of Hf, Zr, Ni, Ta, W, Co, Al, Fe, Mn, Cr, and Nb. An impurity element contained in the resistance change film is at least one element selected from the group consisting of Mg, Ca, Sr, Ba, Sc, Y, La, V, Ta, B, Ga, In, Tl, C, Si, Ge, Sn, Pb, N, P, As, Sb, Bi, S, Se, and Te, and the impurity element has an absolute value of standard Gibbs energy of oxide formation larger than an absolute value of standard Gibbs energy of oxide formation of the element contained in the oxide.
    Type: Application
    Filed: September 16, 2010
    Publication date: March 24, 2011
    Inventors: Kensuke TAKANO, Katsuyuki Sekine, Yoshio Ozawa, Ryota Fujitsuka, Mitsuru Sato
  • Publication number: 20110069530
    Abstract: According to one embodiment, there is provided a method of manufacturing a nonvolatile memory device. In this method, a first voltage may be applied to a variable resistive element having a resistance value which is electrically rewritable in a high resistance and in a low resistance. In this method, a second voltage may be applied to the variable resistive element in a case where the resistance value of the variable resistive element to which the first voltage has been applied is greater than a resistance value of the low resistance and is not greater than a resistance value of the high resistance. Further, in this method, the applying of the second voltage to the variable resistive element may be repeated until the resistance value of the variable resistive element to which the second voltage has been applied falls within a range of the resistance value of the low resistance.
    Type: Application
    Filed: June 25, 2010
    Publication date: March 24, 2011
    Inventors: Katsuyuki SEKINE, Ryota Fujitsuka, Yoshio Ozawa
  • Publication number: 20110049612
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device including a semiconductor layer with a main surface, a first insulating layer formed on the main surface of the semiconductor layer, a charge storage layer formed on the first insulating layer, a second insulating layer formed on the charge storage layer, and a control gate electrode formed on the second insulating layer. At least one inelastic scattering film that reduces energy of electrons by scattering is contained in at least one of the charge storage layer and second insulating layer.
    Type: Application
    Filed: August 12, 2010
    Publication date: March 3, 2011
    Inventors: Masaaki HIGUCHI, Yoshio Ozawa, Katsuyuki Sekine, Ryota Fujitsuka