Abstract: A solid-state image pickup device includes a pixel region including photoelectric conversion units, FDs, and transfer transistors, reset transistors, amplifier transistors, and a reference voltage supply line used to supply reference voltages to the photoelectric conversion units. In the device, the pixel region and the reference voltage supply line are disposed on a first semiconductor substrate, and at least the reset transistors or the amplifier transistors are disposed on a second semiconductor substrate. Furthermore, power supply lines used to supply voltages to the reference voltage supply line are disposed on the second semiconductor substrate. The device further includes second electric connection units which electrically connect the reference voltage supply line to the power supply line. The first electric connection units are disposed in the pixel region whereas the second electric connection units are disposed outside the pixel region.

Abstract: A member for a solid-state image pickup device having a bonding plane with no gaps and a method for manufacturing the same are provided. The manufacturing method includes the steps of providing a first substrate provided with a photoelectric converter on its primary face and a first wiring structure, providing a second substrate provided with a part of a peripheral circuit on its primary face and a second wiring structure, and performing bonding so that the first substrate, the first wiring structure, the second wiring structure, and the second substrate are disposed in this order. In addition, at least one of an upper face of the first wiring structure and an upper face of the second wiring structure has a concave portion, and a conductive material forms a bottom face of the concave portion.

Abstract: A solid-state imaging apparatus, comprising a pixel array in which a plurality of pixels are arrayed, a plurality of processing units, forming a plurality of groups each including two or more processing units, an output line, a power supply line, a plurality of signal lines corresponding to the plurality of groups and connecting output nodes of the two or more processing units in the corresponding group, a plurality of connecting units provided between the output line and the plurality of signal lines, and a control unit configured to control the plurality of processing units and the plurality of connecting units based on a group including the two or more processing units being to output signals.

Abstract: Provided is a solid state imaging apparatus including: a writing memory selecting unit connected between a plurality of vertical output lines and a plurality of memories, configured to selectively store a signal transmitted from at least one of the plurality of vertical output lines into at least one of the plurality of memories; a plurality of horizontal scanning channels configured to input the signals stored in the plurality of memories; and a reading memory selecting unit connected between the plurality of memories and the plurality of horizontal scanning channels, configured to selectively output the signal stored in the at least one of the plurality of memories to at least one of the plurality of horizontal scanning channels. The reading memory selecting unit is configured to output the signals in an order corresponding to spatial arrangement of photoelectric conversion elements.

Abstract: A member for a solid-state image pickup device having a bonding plane with no gaps and a method for manufacturing the same are provided. The manufacturing method includes the steps of providing a first substrate provided with a photoelectric converter on its primary face and a first wiring structure, providing a second substrate provided with a part of a peripheral circuit on its primary face and a second wiring structure, and performing bonding so that the first substrate, the first wiring structure, the second wiring structure, and the second substrate are disposed in this order. In addition, at least one of an upper face of the first wiring structure and an upper face of the second wiring structure has a concave portion, and a conductive material forms a bottom face of the concave portion.

Abstract: Each of a plurality of pixel circuits is an insulated gate transistor and includes a first kind transistor having a maximum value of a gate potential difference to be applied equal to or higher than a first value. Each of a plurality of analog signal processing circuits is an insulated gate transistor and includes a second kind transistor having a maximum value of a gate potential difference to be applied equal to or lower than a second value that is lower than the first value. Each of a plurality of analog signal processing circuits does not include an insulated gate transistor having a maximum value of a gate potential difference to be applied not higher than the second value.

Abstract: First processing of causing a hold unit to hold a first signal from an amplification unit based on reset of the amplification unit, second processing of performing AD conversion of the held first signal and outputting a second signal obtained by superposing a signal based on charges generated in a photoelectric conversion unit of a first-row pixel on the first signal, third processing of performing an operation of performing AD conversion of the held second signal and an operation of resetting the amplification unit at least partly in parallel, and fourth processing of causing the hold unit to hold a fourth signal obtained by superposing a signal based on charges generated in the photoelectric conversion unit of a second-row pixel on a third signal from the amplification unit based on resetting of the amplification unit and is output from the amplification unit are performed.

Abstract: A solid-state imaging apparatus, comprising an imaging unit and a conversion unit, including a first processing unit and a second processing unit, for converting an analog signal output from the imaging unit into a digital signal, wherein the first processing unit generates a higher-order bit of a digital signal corresponding to the analog signal, and the second processing unit, to which a clock signal having a first edge and a second edge is supplied, starts charging a capacitor and ends the charging in response to an elapse of a predetermined time since the first edge of the clock signal supplied immediately after the charging has started, and then generates a lower-order bit of the digital signal.

Abstract: A reed switch 10 includes a cylindrical glass tube 30 and a plurality of reeds 20 fixed to the glass tube 30 in a state where an end side including a contact point portion 22 of each of the reeds 20 is inserted in the glass tube 30. The reeds 20 are each produced by forming, by plastic working, a contact point portion 22 on an end side of a wire for a reed switch. The wire for a reed switch is composed of an iron-group alloy containing, by percent by mass, 1% or more and 10% or less of Fe, 10% or more and 35% or less of Ni, and the balance being Co and impurities and having a cubic crystal structure. The wire has a Curie temperature of 900° C. or higher and a wire diameter of 1 mm or less. The wire is composed of a ternary alloy having a particular composition. Therefore, the wire has a high Curie temperature, a low resistance, and a particular structure and thus has good workability.

Abstract: An object of the present invention is to provide a comparator which has an input voltage range larger than the case where a conventional offset cancel technique is used, while reducing an offset voltage. A comparator circuit includes: a comparator having an inverting input terminal, a non-inverting input terminal and an output terminal; a first switch having one terminal connected to the inverting input terminal and having the other terminal connected to the output terminal; a first capacitor which has one end connected with the inverting input terminal; a first signal input terminal which is another end of the first capacitor; and a second signal input terminal which selectively inputs either one of a fixed voltage and a comparing signal into the non-inverting input terminal.

Abstract: The present invention relates to a solid-state image pickup device. The device includes a first substrate including a photoelectric conversion element and a transfer gate electrode configured to transfer charge from the photoelectric conversion element, a second substrate having a peripheral circuit portion including a circuit configured to read a signal based charge generated in the photoelectric conversion element, the first and second substrates being laminated. The device further includes a multilayer interconnect structure, disposed on the first substrate, including an aluminum interconnect and a multilayer interconnect structure, disposed on the second substrate, including a copper interconnect.

Abstract: In a solid-state imaging device, a photoelectric conversion unit, a transfer transistor, and at least a part of electric charge holding unit, among pixel constituent elements, are disposed on a first semiconductor substrate. An amplifying transistor, a signal processing circuit other than a reset transistor, and a plurality of common output lines, to which signals are read out from a plurality of pixels, are disposed on a second semiconductor substrate.

Abstract: A solid-state imaging apparatus includes a pixel section in which a plurality of pixels are arranged in a matrix, a column signal line configured to output a pixel signal from the pixel section, a column amplifier circuit configured to invert and amplify the pixel signal, a bypass circuit configured to bypass the column amplifier circuit, an AD converter, and a control unit configured to change an operation mode of the AD converter in accordance with the operation of the bypass circuit.

Abstract: A solid-state imaging device is configured such that an effective pixel and a reference pixel are connected to first and second signal lines, respectively. The solid-state imaging device includes a difference signal output unit configured to perform difference processing on a signal output from a first amplifying transistor included in the effective pixel and a signal output from a second amplifying transistor included in the reference pixel. The difference signal output unit is provided separately from the first and second amplifying transistors.

Abstract: A controller for a conventional synchronous motor is configured to produce desired output characteristics. The controller generates a drive current for based on a current command, has a motor correcting section and a gain adjusting section which output a compensated current command based on the current command according to a compensating transfer function for cancelling a first transfer function showing a first torque response characteristic of the synchronous motor and replacing it with a second transfer function showing a second torque response characteristic, and a current controller which generates a drive current corresponding to the compensated current command.

Abstract: An imaging system includes an A/D converter including a holding unit holding a pixel signal as a voltage level, a comparator comparing the voltage level held with a reference level, a circuit capable of changing the voltage level so as to approach the reference level at first and second rates, wherein the voltage level is changed at the first rate to determine higher bits in accordance with inversion of a relationship between the reference level and the voltage level, after that, the voltage level is changed at the second rate to determine lower bits in accordance with inversion of the relationship between the reference level and the voltage level, and an adjusting unit which adjusts the voltage level during a period until the voltage level is changed at the second rate after determination of the higher bits so that the lower bits and the voltage level hold a linear relationship.

Abstract: In a solid-state imaging device, a photoelectric conversion unit, a transfer transistor, and at least a part of electric charge holding unit, among pixel constituent elements, are disposed on a first semiconductor substrate. An amplifying transistor, a signal processing circuit other than a reset transistor, and a plurality of common output lines, to which signals are read out from a plurality of pixels, are disposed on a second semiconductor substrate.

Abstract: A reinstalling method which, when reinstalling an object to be supported, precisely restores the object to an initial installing state in a short period of time without requiring special skills. In a state before supporting of an object to be supported by support tools is released and in each of states in which the supporting is sequentially released, load acting on at least one support tool selected from among the support tools being in a supporting state is obtained. When reinstalling, the object is sequentially supported at the same positions as those before the release by the support tools in the reverse order to that of the release, and, a vertical-direction supporting position of each support tool is adjusted so that a load cell of the selected support tool detects the same value as the load obtained in the supporting state before the support tool was released.

Abstract: Column signal processing units are provided in correspondence with respective columns of a pixel array. The column signal processing unit includes a sample-and-hold unit configured to hold an analog signal output from a pixel, a buffer unit configured to buffer the signal held in the sample-and-hold unit, and an AD conversion unit. The AD conversion unit converts the signal held by the sample-and-hold unit and buffered by the buffer unit into a digital signal.

Abstract: An oxide film is formed on the surface of a sample made from a metal material by holding the above-described sample at a temperature of 800° C. or higher and 1,100° C. or lower in an oxygen-containing atmosphere, and the sample provided with the oxide film is immersed in a corrosive solution containing an acid and NaCl for a predetermined time. After immersion, the corrosion state (degree of denseness of oxide film, cracking state, and the like) of the sample is evaluated. The corrosion resistance of the sample can be evaluated appropriately and conveniently in a short period of time by causing accelerated corrosion in an environment simulating the actual environment of an internal combustion engine.