Patents by Inventor Kazuo Yamazaki

Kazuo Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160209828
    Abstract: A machine tool includes a bed supported on a ground by supporting jigs, a table movable in an X-axis direction, a spindle head movable in a Y-axis direction, a quill provided to be movable in a Z-axis direction, a spindle supported by the quill to be rotatable about its axis, feed mechanisms for moving the table and the like in the axis directions, and a numerical controller controlling operation of the feed mechanisms, and the numerical controller is configured to calculate motion errors based on load values acting on the supporting jigs by a motion locus estimator, an influence coefficient storage, a motion error calculator, and a motion locus storage, generate a correction signal for compensating for the motion errors by a position corrector, and add the generated correction signals to a position control signal transmitted from a position generator to a position controller.
    Type: Application
    Filed: January 12, 2016
    Publication date: July 21, 2016
    Applicant: DMG MORI CO., LTD.
    Inventors: Hidenori Saraie, Kinji Hashimoto, Keiichiro Matsuo, Kazuo Yamazaki, Toshiya Sato
  • Patent number: 9385152
    Abstract: The present invention relates to a solid-state image pickup device. The device includes a first substrate including a photoelectric conversion element and a transfer gate electrode configured to transfer charge from the photoelectric conversion element, a second substrate having a peripheral circuit portion including a circuit configured to read a signal based charge generated in the photoelectric conversion element, the first and second substrates being laminated. The device further includes a multilayer interconnect structure, disposed on the first substrate, including an aluminum interconnect and a multilayer interconnect structure, disposed on the second substrate, including a copper interconnect.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: July 5, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Nobuyuki Endo, Tetsuya Itano, Kazuo Yamazaki, Kyouhei Watanabe, Takeshi Ichikawa
  • Publication number: 20160175946
    Abstract: A milling cutter is composed of a tool body having an approximately cylindrical or disk-like shape and a plurality of edge portions provided on at least an outer peripheral portion of one end of the tool body at predetermined intervals along a circumferential direction. The edge portion has a major cutting edge and a minor cutting edge that perform an operation of cutting a workpiece, the major cutting edge is positioned outside the minor cutting edge in a radial direction, and the minor cutting edge has a cutting edge angle that is an angle with respect to a plane orthogonal to a center axis of the tool body and set so as to be an elevation angle open outward in the radial direction. When surface machining is performed on a workpiece with the milling cutter, a high degree of machined surface accuracy equivalent to that obtained by grinding is obtained.
    Type: Application
    Filed: December 4, 2015
    Publication date: June 23, 2016
    Applicants: DMG MORI CO., LTD., Intelligent Manufacturing Systems International, Advanced Research for Manufacturing Systems, LLC
    Inventors: Hidenori Saraie, Eisaku Ueda, Masaya Nishimoto, Kazuo Yamazaki, Masakazu Soshi
  • Publication number: 20160167201
    Abstract: A workpiece fixing jig 1 includes a base 2 to be fixed on a table, and a clamping mechanism 10 provided on the base 2 for clamping a workpiece. The clamping mechanism 10 includes a first clamping portion 20 and a second clamping portion 30 provided to face each other. At least one of the first and second clamping portions 20 and 30 is configured to move forward and backward with respect to the other along a moving direction and the moving direction is set to a direction intersecting a direction in which the base 2 is fixed on the table. In using this workpiece fixing jig 1, the base 2 is fixed on the table after the workpiece is clamped between the first clamping portion 20 and the second clamping portion 30.
    Type: Application
    Filed: November 18, 2015
    Publication date: June 16, 2016
    Applicants: INTELLIGENT MANUFACTURING SYSTEMS INTERNATIONAL, DMG MORI CO., LTD.
    Inventors: Hidenori Saraie, Kinji Hashimoto, Kazuo Yamazaki
  • Publication number: 20160156868
    Abstract: A solid-state imaging apparatus includes a pixel section in which a plurality of pixels are arranged in a matrix, a column signal line configured to output a pixel signal from the pixel section, a column amplifier circuit configured to invert and amplify the pixel signal, a bypass circuit configured to bypass the column amplifier circuit, an AD converter, and a control unit configured to change an operation mode of the AD converter in accordance with the operation of the bypass circuit.
    Type: Application
    Filed: February 2, 2016
    Publication date: June 2, 2016
    Inventors: Kazuo Yamazaki, Tetsuya Itano, Hiroki Hiyama
  • Patent number: 9344652
    Abstract: Column signal processing units are provided in correspondence with respective columns of a pixel array. The column signal processing unit includes a sample-and-hold unit configured to hold an analog signal output from a pixel, a buffer unit configured to buffer the signal held in the sample-and-hold unit, and an AD conversion unit. The AD conversion unit converts the signal held by the sample-and-hold unit and buffered by the buffer unit into a digital signal.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: May 17, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Tetsuya Itano, Kazuo Yamazaki, Kohichi Nakamura, Koichiro Iwata, Yasuji Ikeda
  • Patent number: 9338377
    Abstract: Dark current from a transfer transistor is suppressed and power-supply voltage in a second semiconductor substrate is lowered. A solid-state image pickup device includes a pixel array, a plurality of common output lines receiving signals read out from a plurality of pixels, a transfer scanning unit sequentially driving the plurality of transfer transistors, a signal processing unit processing the signals output to the common signal lines, and a level shift unit making amplitude of a pulse supplied to a gate of the transfer transistor larger than amplitude of a pulse supplied to a gate of a transistor constituting the signal processing unit. The pixel array and the level shift unit are arranged on a first semiconductor substrate, whereas the plurality of common output lines and the signal processing unit are arranged on a second semiconductor substrate.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: May 10, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Tetsuya Itano, Kazuo Yamazaki, Nobuyuki Endo, Kyouhei Watanabe
  • Publication number: 20160127669
    Abstract: An apparatus including pixels, each having first and second photoelectric conversion elements, an amplifying unit, first and second transfer gates, and a microlens, performs, in one pixel, a first operation involving turning on the first transfer gate, outputting a signal based on charge generated in the first photoelectric conversion element, turning on the first and second transfer gates while retaining the charge generated and transferred to an input node, and outputting a signal based on charges generated in the first and second photoelectric conversion elements, and, in another pixel, a second operation involving turning on the first transfer gate, not outputting a signal based on charge generated in the first photoelectric conversion element, turning on the first and second transfer gates while retaining the charge generated and transferred to the input node, and outputting a signal based on charges generated in the first and second photoelectric conversion elements.
    Type: Application
    Filed: November 2, 2015
    Publication date: May 5, 2016
    Inventor: Kazuo Yamazaki
  • Patent number: 9288415
    Abstract: A solid-state imaging apparatus includes a pixel section in which a plurality of pixels are arranged in a matrix, a column signal line configured to output a pixel signal from the pixel section, a column amplifier circuit configured to invert and amplify the pixel signal, a bypass circuit configured to bypass the column amplifier circuit, an AD converter, and a control unit configured to change an operation mode of the AD converter in accordance with the operation of the bypass circuit.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: March 15, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuo Yamazaki, Tetsuya Itano, Hiroki Hiyama
  • Patent number: 9258499
    Abstract: An apparatus includes a pixel array in which pixels for outputting an analog signal are arranged in a matrix, vertical output lines each of which is connected to pixels in a same column, A/D conversion units, which are individually connected to the vertical output lines, for converting the analog signal into a digital signal, and a constant current supply unit for supplying a constant current to the A/D conversion units. Each of the A/D conversion units includes an integration unit for integrating the constant current, a comparison unit for comparing the integrated constant current with the analog signal and outputting a comparison signal, and a digital signal storage unit for storing a digital signal corresponding to the comparison signal. The integration unit includes an input capacitor for receiving the constant current. The comparison unit is connected to the constant current supply unit via the input capacitor.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 9, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hiroki Hiyama, Masaaki Iwane, Kazuo Yamazaki
  • Patent number: 9247173
    Abstract: Each of a plurality of pixel circuits is an insulated gate transistor and includes a first kind transistor having a maximum value of a gate potential difference to be applied equal to or higher than a first value. Each of a plurality of analog signal processing circuits is an insulated gate transistor and includes a second kind transistor having a maximum value of a gate potential difference to be applied equal to or lower than a second value that is lower than the first value. Each of a plurality of analog signal processing circuits does not include an insulated gate transistor having a maximum value of a gate potential difference to be applied not higher than the second value.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: January 26, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Kazuo Kokumai, Yusuke Onuki, Hiroaki Naruse, Masashi Kusukawa, Katsunori Hirota, Nobuyuki Endo, Kazuo Yamazaki, Hiroaki Kobayashi
  • Publication number: 20160013236
    Abstract: An apparatus according to the present invention in which a first substrate including a photoelectric conversion element and a gate electrode of a transistor, and a second substrate including a peripheral circuit portion are placed upon each other. The first substrate does not include a high-melting-metal compound layer, and the second substrate includes a high-melting-metal compound layer.
    Type: Application
    Filed: September 22, 2015
    Publication date: January 14, 2016
    Inventors: Nobuyuki Endo, Tetsuya Itano, Kazuo Yamazaki, Kyouhei Watanabe, Takeshi Ichikawa
  • Publication number: 20160006968
    Abstract: Provided is an imaging apparatus and an imaging system that can suppress high-brightness darkening phenomenon without preventing achievement of high-speed operation. The imaging apparatus includes: pixels each outputting a signal based on photoelectric conversion to each of signal lines; clip units each having a first transistor for clipping the voltage of each of the signal lines; a holding capacitor having a first electrode connected to a control electrode of the first transistor, and having a second electrode; a shift unit configured to supply, to the second electrodes, a plurality of voltages having values different from each other; and a voltage supplying unit provided separately from the shift unit and supplying a first voltage to the second electrodes.
    Type: Application
    Filed: June 24, 2015
    Publication date: January 7, 2016
    Inventors: Seiichirou Sakai, Hiroki Hiyama, Kazuo Yamazaki
  • Publication number: 20160006956
    Abstract: During a period in which an electric potential of one node of a holding capacitance shifts from a first electric potential to a second electric potential, the other node of the holding capacitance is in an electrically-floating state.
    Type: Application
    Filed: June 30, 2015
    Publication date: January 7, 2016
    Inventors: Seiichirou Sakai, Hiroki Hiyama, Kazuo Yamazaki
  • Patent number: 9221140
    Abstract: A workpiece is machined by setting a frequency response band of a control system for a rotation drive motor or a feed drive motor so that tool abrasion is within a predetermined allowable range. The frequency response band may be adjusted by adjusting a proportional gain and an integral gain. With the workpiece machined by such a process, where the frequency response band maintains tool abrasion within the allowable range, machining quality and efficiency are improved.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: December 29, 2015
    Assignees: DMG MORI SEIKI CO., LTD., INTELLIGENT MANUFACUTRING SYSTEMS INTERNATIONAL
    Inventors: Masakazu Soshi, Shinji Ishii, Kazuo Yamazaki
  • Patent number: 9204072
    Abstract: A photoelectric conversion device includes a pixel array including a plurality of pixels arranged in a matrix, a plurality of blocks including a plurality of pairs, each of the pairs including a comparator provided correspondingly with a column in the pixel array and a memory provided correspondingly with the comparator, and a block information supply unit configured to supply block information which indicates a location of a block, to the plurality of memories included in the blocks.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: December 1, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroki Hiyama, Kohichi Nakamura, Kazuo Yamazaki, Kazuhiro Saito
  • Patent number: 9204066
    Abstract: A solid-state imaging device has a configuration for selecting from a plurality of reference pixels at least one reference pixel for outputting a reference signal.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: December 1, 2015
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Kazuaki Tashiro, Kazuo Yamazaki
  • Publication number: 20150341580
    Abstract: In an imaging device including a pixel array in which a plurality of pixels is arranged, each of the pixels including first and second photoelectric conversion units, and a micro lens that collects incident light to the first and second photoelectric conversion units, in a first frame period, a first signal based on a signal electric charge generated in the first photoelectric conversion unit and a second signal based on a signal electric charge generated in at least the second photoelectric conversion unit are read out from a plurality of pixels included in a part of the pixel array, and in a second frame period, a third signal based on the signal electric charges generated in the first and the second photoelectric conversion units is read out from a plurality of pixels included in another part of the pixel array.
    Type: Application
    Filed: May 12, 2015
    Publication date: November 26, 2015
    Inventors: Kazuo Yamazaki, Seiichirou Sakai, Yu Maehashi
  • Publication number: 20150330922
    Abstract: A sample composed of a nickel-based metal is immersed in a corrosive solution (aqueous solution containing an acid and sodium chloride). The sample that has been immersed in the corrosive solution is exposed to a flame of engine oil, and further heated. By immersing the sample in the particular corrosive solution, a Ni-enriched phase which is deficient in additional elements and in which the Ni concentration increases is formed in a surface layer region of the sample. By exposing the sample having the Ni-enriched phase to the flame of the engine oil, components in the engine oil are activated and brought into contact with the sample to form a low-melting point phase in the surface layer region of the sample. By heating the sample having the low-melting point phase to melt the low-melting point phase and resolidifying the low-melting point phase, particles and the like can be formed depending on the type of material of the sample.
    Type: Application
    Filed: November 4, 2013
    Publication date: November 19, 2015
    Inventors: Hajime OTA, Taichiro NISHIKAWA, Kazuo YAMAZAKI, Masao SAKUTA, Takeshi TOKUDA
  • Patent number: 9178081
    Abstract: An apparatus according to the present invention in which a first substrate including a photoelectric conversion element and a gate electrode of a transistor, and a second substrate including a peripheral circuit portion are placed upon each other. The first substrate does not include a high-melting-metal compound layer, and the second substrate includes a high-melting-metal compound layer.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: November 3, 2015
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Nobuyuki Endo, Tetsuya Itano, Kazuo Yamazaki, Kyouhei Watanabe, Takeshi Ichikawa