Patents by Inventor Kazuo Yamazaki

Kazuo Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9509931
    Abstract: A solid-state imaging apparatus, comprising a pixel array in which a plurality of pixels are arrayed, a plurality of processing units, forming a plurality of groups each including two or more processing units, an output line, a power supply line, a plurality of signal lines corresponding to the plurality of groups and connecting output nodes of the two or more processing units in the corresponding group, a plurality of connecting units provided between the output line and the plurality of signal lines, and a control unit configured to control the plurality of processing units and the plurality of connecting units based on a group including the two or more processing units being to output signals.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: November 29, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideo Kobayashi, Hiroki Hiyama, Kazuo Yamazaki, Hiroaki Kameyama
  • Publication number: 20160309101
    Abstract: Dark current from a transfer transistor is suppressed and power-supply voltage in a second semiconductor substrate is lowered. A solid-state image pickup device includes a pixel array, a plurality of common output lines receiving signals read out from a plurality of pixels, a transfer scanning unit sequentially driving the plurality of transfer transistors, a signal processing unit processing the signals output to the common signal lines, and a level shift unit making amplitude of a pulse supplied to a gate of the transfer transistor larger than amplitude of a pulse supplied to a gate of a transistor constituting the signal processing unit. The pixel array and the level shift unit are arranged on a first semiconductor substrate, whereas the plurality of common output lines and the signal processing unit are arranged on a second semiconductor substrate.
    Type: Application
    Filed: April 13, 2016
    Publication date: October 20, 2016
    Inventors: Tetsuya Itano, Kazuo Yamazaki, Nobuyuki Endo, Kyouhei Watanabe
  • Patent number: 9456161
    Abstract: An apparatus including pixels, each having first and second photoelectric conversion elements, an amplifying unit, first and second transfer gates, and a microlens, performs, in one pixel, a first operation involving turning on the first transfer gate, outputting a signal based on charge generated in the first photoelectric conversion element, turning on the first and second transfer gates while retaining the charge generated and transferred to an input node, and outputting a signal based on charges generated in the first and second photoelectric conversion elements, and, in another pixel, a second operation involving turning on the first transfer gate, not outputting a signal based on charge generated in the first photoelectric conversion element, turning on the first and second transfer gates while retaining the charge generated and transferred to the input node, and outputting a signal based on charges generated in the first and second photoelectric conversion elements.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: September 27, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Kazuo Yamazaki
  • Publication number: 20160277695
    Abstract: A solid-state imaging device includes a pixel including a photoelectric conversion element, an accumulation unit accumulating charges generated by the photoelectric conversion element, a reset unit resetting the accumulation unit at a voltage of equal to or more than 4.05 V, and an amplifier transistor amplifying and outputting a signal corresponding to amount of accumulated charges, a vertical output line connected to the pixel, a current source circuit including first to third transistors flowing a constant current through the vertical output line, and a voltage setting circuit respectively setting the gate voltages of the first to third transistors to a first voltage, a second voltage higher than the first voltage, and a third voltage higher than the second voltage and lower than the power supply voltage so as to set the drain-source voltage of each of the first to third transistors to equal to or less than 1.75 V.
    Type: Application
    Filed: February 29, 2016
    Publication date: September 22, 2016
    Inventors: Yasuhiro Oguro, Kazuo Yamazaki, Seiichirou Sakai
  • Patent number: 9443895
    Abstract: An apparatus according to the present invention in which a first substrate including a photoelectric conversion element and a gate electrode of a transistor, and a second substrate including a peripheral circuit portion are placed upon each other. The first substrate does not include a high-melting-metal compound layer, and the second substrate includes a high-melting-metal compound layer.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: September 13, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Nobuyuki Endo, Tetsuya Itano, Kazuo Yamazaki, Kyouhei Watanabe, Takeshi Ichikawa
  • Patent number: 9438841
    Abstract: A solid-state imaging apparatus includes a pixel section in which a plurality of pixels are arranged in a matrix, a column signal line configured to output a pixel signal from the pixel section, a column amplifier circuit configured to invert and amplify the pixel signal, a bypass circuit configured to bypass the column amplifier circuit, an AD converter, and a control unit configured to change an operation mode of the AD converter in accordance with the operation of the bypass circuit.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: September 6, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuo Yamazaki, Tetsuya Itano, Hiroki Hiyama
  • Publication number: 20160255248
    Abstract: An electronic circuit includes a generating circuit for generating a first group of signals and a second group of signals, and a transmission path for transmitting the first group of signals and the second group of signals. The first group of signals are composed of signals synchronized with a first edge that is one of the rising edge and the falling edge of a reference clock, and the second group of signals are composed of signals synchronized with a second edge that is the other of the rising edge and falling edge. The transmission path includes first transmission lines for transmitting the signals composing the first group and second transmission lines for transmitting the signals composing the second group, and the first and second transmission lines are alternately arranged.
    Type: Application
    Filed: February 16, 2016
    Publication date: September 1, 2016
    Inventors: Hideo Kobayashi, Kazuo Yamazaki, Hiroki Hiyama
  • Patent number: 9407847
    Abstract: Provided is a solid state imaging apparatus including: a writing memory selecting unit connected between a plurality of vertical output lines and a plurality of memories, configured to selectively store a signal transmitted from at least one of the plurality of vertical output lines into at least one of the plurality of memories; a plurality of horizontal scanning channels configured to input the signals stored in the plurality of memories; and a reading memory selecting unit connected between the plurality of memories and the plurality of horizontal scanning channels, configured to selectively output the signal stored in the at least one of the plurality of memories to at least one of the plurality of horizontal scanning channels. The reading memory selecting unit is configured to output the signals in an order corresponding to spatial arrangement of photoelectric conversion elements.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: August 2, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yu Maehashi, Hiroaki Kameyama, Hideo Kobayashi, Kazuo Yamazaki
  • Publication number: 20160209828
    Abstract: A machine tool includes a bed supported on a ground by supporting jigs, a table movable in an X-axis direction, a spindle head movable in a Y-axis direction, a quill provided to be movable in a Z-axis direction, a spindle supported by the quill to be rotatable about its axis, feed mechanisms for moving the table and the like in the axis directions, and a numerical controller controlling operation of the feed mechanisms, and the numerical controller is configured to calculate motion errors based on load values acting on the supporting jigs by a motion locus estimator, an influence coefficient storage, a motion error calculator, and a motion locus storage, generate a correction signal for compensating for the motion errors by a position corrector, and add the generated correction signals to a position control signal transmitted from a position generator to a position controller.
    Type: Application
    Filed: January 12, 2016
    Publication date: July 21, 2016
    Applicant: DMG MORI CO., LTD.
    Inventors: Hidenori Saraie, Kinji Hashimoto, Keiichiro Matsuo, Kazuo Yamazaki, Toshiya Sato
  • Patent number: 9385152
    Abstract: The present invention relates to a solid-state image pickup device. The device includes a first substrate including a photoelectric conversion element and a transfer gate electrode configured to transfer charge from the photoelectric conversion element, a second substrate having a peripheral circuit portion including a circuit configured to read a signal based charge generated in the photoelectric conversion element, the first and second substrates being laminated. The device further includes a multilayer interconnect structure, disposed on the first substrate, including an aluminum interconnect and a multilayer interconnect structure, disposed on the second substrate, including a copper interconnect.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: July 5, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Nobuyuki Endo, Tetsuya Itano, Kazuo Yamazaki, Kyouhei Watanabe, Takeshi Ichikawa
  • Publication number: 20160175946
    Abstract: A milling cutter is composed of a tool body having an approximately cylindrical or disk-like shape and a plurality of edge portions provided on at least an outer peripheral portion of one end of the tool body at predetermined intervals along a circumferential direction. The edge portion has a major cutting edge and a minor cutting edge that perform an operation of cutting a workpiece, the major cutting edge is positioned outside the minor cutting edge in a radial direction, and the minor cutting edge has a cutting edge angle that is an angle with respect to a plane orthogonal to a center axis of the tool body and set so as to be an elevation angle open outward in the radial direction. When surface machining is performed on a workpiece with the milling cutter, a high degree of machined surface accuracy equivalent to that obtained by grinding is obtained.
    Type: Application
    Filed: December 4, 2015
    Publication date: June 23, 2016
    Applicants: DMG MORI CO., LTD., Intelligent Manufacturing Systems International, Advanced Research for Manufacturing Systems, LLC
    Inventors: Hidenori Saraie, Eisaku Ueda, Masaya Nishimoto, Kazuo Yamazaki, Masakazu Soshi
  • Publication number: 20160167201
    Abstract: A workpiece fixing jig 1 includes a base 2 to be fixed on a table, and a clamping mechanism 10 provided on the base 2 for clamping a workpiece. The clamping mechanism 10 includes a first clamping portion 20 and a second clamping portion 30 provided to face each other. At least one of the first and second clamping portions 20 and 30 is configured to move forward and backward with respect to the other along a moving direction and the moving direction is set to a direction intersecting a direction in which the base 2 is fixed on the table. In using this workpiece fixing jig 1, the base 2 is fixed on the table after the workpiece is clamped between the first clamping portion 20 and the second clamping portion 30.
    Type: Application
    Filed: November 18, 2015
    Publication date: June 16, 2016
    Applicants: INTELLIGENT MANUFACTURING SYSTEMS INTERNATIONAL, DMG MORI CO., LTD.
    Inventors: Hidenori Saraie, Kinji Hashimoto, Kazuo Yamazaki
  • Publication number: 20160156868
    Abstract: A solid-state imaging apparatus includes a pixel section in which a plurality of pixels are arranged in a matrix, a column signal line configured to output a pixel signal from the pixel section, a column amplifier circuit configured to invert and amplify the pixel signal, a bypass circuit configured to bypass the column amplifier circuit, an AD converter, and a control unit configured to change an operation mode of the AD converter in accordance with the operation of the bypass circuit.
    Type: Application
    Filed: February 2, 2016
    Publication date: June 2, 2016
    Inventors: Kazuo Yamazaki, Tetsuya Itano, Hiroki Hiyama
  • Patent number: 9344652
    Abstract: Column signal processing units are provided in correspondence with respective columns of a pixel array. The column signal processing unit includes a sample-and-hold unit configured to hold an analog signal output from a pixel, a buffer unit configured to buffer the signal held in the sample-and-hold unit, and an AD conversion unit. The AD conversion unit converts the signal held by the sample-and-hold unit and buffered by the buffer unit into a digital signal.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: May 17, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Tetsuya Itano, Kazuo Yamazaki, Kohichi Nakamura, Koichiro Iwata, Yasuji Ikeda
  • Patent number: 9338377
    Abstract: Dark current from a transfer transistor is suppressed and power-supply voltage in a second semiconductor substrate is lowered. A solid-state image pickup device includes a pixel array, a plurality of common output lines receiving signals read out from a plurality of pixels, a transfer scanning unit sequentially driving the plurality of transfer transistors, a signal processing unit processing the signals output to the common signal lines, and a level shift unit making amplitude of a pulse supplied to a gate of the transfer transistor larger than amplitude of a pulse supplied to a gate of a transistor constituting the signal processing unit. The pixel array and the level shift unit are arranged on a first semiconductor substrate, whereas the plurality of common output lines and the signal processing unit are arranged on a second semiconductor substrate.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: May 10, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Tetsuya Itano, Kazuo Yamazaki, Nobuyuki Endo, Kyouhei Watanabe
  • Publication number: 20160127669
    Abstract: An apparatus including pixels, each having first and second photoelectric conversion elements, an amplifying unit, first and second transfer gates, and a microlens, performs, in one pixel, a first operation involving turning on the first transfer gate, outputting a signal based on charge generated in the first photoelectric conversion element, turning on the first and second transfer gates while retaining the charge generated and transferred to an input node, and outputting a signal based on charges generated in the first and second photoelectric conversion elements, and, in another pixel, a second operation involving turning on the first transfer gate, not outputting a signal based on charge generated in the first photoelectric conversion element, turning on the first and second transfer gates while retaining the charge generated and transferred to the input node, and outputting a signal based on charges generated in the first and second photoelectric conversion elements.
    Type: Application
    Filed: November 2, 2015
    Publication date: May 5, 2016
    Inventor: Kazuo Yamazaki
  • Patent number: 9288415
    Abstract: A solid-state imaging apparatus includes a pixel section in which a plurality of pixels are arranged in a matrix, a column signal line configured to output a pixel signal from the pixel section, a column amplifier circuit configured to invert and amplify the pixel signal, a bypass circuit configured to bypass the column amplifier circuit, an AD converter, and a control unit configured to change an operation mode of the AD converter in accordance with the operation of the bypass circuit.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: March 15, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuo Yamazaki, Tetsuya Itano, Hiroki Hiyama
  • Patent number: 9258499
    Abstract: An apparatus includes a pixel array in which pixels for outputting an analog signal are arranged in a matrix, vertical output lines each of which is connected to pixels in a same column, A/D conversion units, which are individually connected to the vertical output lines, for converting the analog signal into a digital signal, and a constant current supply unit for supplying a constant current to the A/D conversion units. Each of the A/D conversion units includes an integration unit for integrating the constant current, a comparison unit for comparing the integrated constant current with the analog signal and outputting a comparison signal, and a digital signal storage unit for storing a digital signal corresponding to the comparison signal. The integration unit includes an input capacitor for receiving the constant current. The comparison unit is connected to the constant current supply unit via the input capacitor.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 9, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hiroki Hiyama, Masaaki Iwane, Kazuo Yamazaki
  • Patent number: 9247173
    Abstract: Each of a plurality of pixel circuits is an insulated gate transistor and includes a first kind transistor having a maximum value of a gate potential difference to be applied equal to or higher than a first value. Each of a plurality of analog signal processing circuits is an insulated gate transistor and includes a second kind transistor having a maximum value of a gate potential difference to be applied equal to or lower than a second value that is lower than the first value. Each of a plurality of analog signal processing circuits does not include an insulated gate transistor having a maximum value of a gate potential difference to be applied not higher than the second value.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: January 26, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Kazuo Kokumai, Yusuke Onuki, Hiroaki Naruse, Masashi Kusukawa, Katsunori Hirota, Nobuyuki Endo, Kazuo Yamazaki, Hiroaki Kobayashi
  • Publication number: 20160013236
    Abstract: An apparatus according to the present invention in which a first substrate including a photoelectric conversion element and a gate electrode of a transistor, and a second substrate including a peripheral circuit portion are placed upon each other. The first substrate does not include a high-melting-metal compound layer, and the second substrate includes a high-melting-metal compound layer.
    Type: Application
    Filed: September 22, 2015
    Publication date: January 14, 2016
    Inventors: Nobuyuki Endo, Tetsuya Itano, Kazuo Yamazaki, Kyouhei Watanabe, Takeshi Ichikawa