Patents by Inventor Kazuo Yamazaki

Kazuo Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9702838
    Abstract: A sample composed of a nickel-based metal is immersed in a corrosive solution (aqueous solution containing an acid and sodium chloride). The sample that has been immersed in the corrosive solution is exposed to a flame of engine oil, and further heated. By immersing the sample in the particular corrosive solution, a Ni-enriched phase which is deficient in additional elements and in which the Ni concentration increases is formed in a surface layer region of the sample. By exposing the sample having the Ni-enriched phase to the flame of the engine oil, components in the engine oil are activated and brought into contact with the sample to form a low-melting point phase in the surface layer region of the sample. By heating the sample having the low-melting point phase to melt the low-melting point phase and resolidifying the low-melting point phase, particles and the like can be formed depending on the type of material of the sample.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: July 11, 2017
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hajime Ota, Taichiro Nishikawa, Kazuo Yamazaki, Masao Sakuta, Takeshi Tokuda
  • Patent number: 9704915
    Abstract: A member for a solid-state image pickup device having a bonding plane with no gaps and a method for manufacturing the same are provided. The manufacturing method includes the steps of providing a first substrate provided with a photoelectric converter on its primary face and a first wiring structure, providing a second substrate provided with a part of a peripheral circuit on its primary face and a second wiring structure, and performing bonding so that the first substrate, the first wiring structure, the second wiring structure, and the second substrate are disposed in this order. In addition, at least one of an upper face of the first wiring structure and an upper face of the second wiring structure has a concave portion, and a conductive material forms a bottom face of the concave portion.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: July 11, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Nobuyuki Endo, Tetsuya Itano, Kazuo Yamazaki, Kyouhei Watanabe, Junji Iwata
  • Publication number: 20170171489
    Abstract: A signal based on a pixel signal of a first pixel sampled by a capacitor element is held by a signal holding unit with a switch left turned on.
    Type: Application
    Filed: December 7, 2016
    Publication date: June 15, 2017
    Inventors: Hideo Kobayashi, Kazuo Yamazaki, Kei Ochiai, Masaki Sato
  • Publication number: 20170171486
    Abstract: A photoelectric convertor of a pixel is reset in a second row, which is different from a first row, among plural rows during a period in which the pixel in the first row among the plural rows is being selected as a pixel to output an optical signal. The reset of the photoelectric convertor of the pixel in the second row is canceled in a period other than a period in which an A/D converting unit converts the optical signal of the pixel in the first row into a digital signal.
    Type: Application
    Filed: December 7, 2016
    Publication date: June 15, 2017
    Inventors: Kei Ochiai, Hideo Kobayashi, Kazuo Yamazaki, Yasuhiro Oguro, Masaki Sato, Mineo Uchida
  • Patent number: 9681076
    Abstract: A solid-state imaging device includes a pixel including a photoelectric conversion element, an accumulation unit accumulating charges generated by the photoelectric conversion element, a reset unit resetting the accumulation unit at a voltage of equal to or more than 4.05 V, and an amplifier transistor amplifying and outputting a signal corresponding to amount of accumulated charges, a vertical output line connected to the pixel, a current source circuit including first to third transistors flowing a constant current through the vertical output line, and a voltage setting circuit respectively setting the gate voltages of the first to third transistors to a first voltage, a second voltage higher than the first voltage, and a third voltage higher than the second voltage and lower than the power supply voltage so as to set the drain-source voltage of each of the first to third transistors to equal to or less than 1.75 V.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: June 13, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yasuhiro Oguro, Kazuo Yamazaki, Seiichirou Sakai
  • Publication number: 20170155839
    Abstract: An image pickup apparatus includes a pixel array including a plurality of pixels arranged in a plurality of rows and a plurality of columns, and a plurality of column signal processing circuits provided respectively for the columns of the pixel array, each being configured to receive output signals from the pixels and an analog signal varying with time. The plurality of column signal processing circuits include a first column signal processing circuit and a second column signal processing circuit configured such that each of the first column signal processing circuit and the second column signal processing circuit is configured to be independently switched between a driving state and a power saving state. A signal line for supplying the analog signal to the first column signal processing circuit and a signal line for supplying the analog signal to the second column signal processing circuit are electrically isolated from each other.
    Type: Application
    Filed: November 23, 2016
    Publication date: June 1, 2017
    Inventors: Kazuo Yamazaki, Seiichirou Sakai, Yasuhiro Oguro
  • Patent number: 9666621
    Abstract: In a solid-state imaging device, a photoelectric conversion unit, a transfer transistor, and at least a part of electric charge holding unit, among pixel constituent elements, are disposed on a first semiconductor substrate. An amplifying transistor, a signal processing circuit other than a reset transistor, and a plurality of common output lines, to which signals are read out from a plurality of pixels, are disposed on a second semiconductor substrate.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: May 30, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Kazuo Yamazaki, Tetsuya Itano, Nobuyuki Endo, Kyouhei Watanabe
  • Patent number: 9667901
    Abstract: Provided is an imaging apparatus and an imaging system that can suppress high-brightness darkening phenomenon without preventing achievement of high-speed operation. The imaging apparatus includes: pixels each outputting a signal based on photoelectric conversion to each of signal lines; clip units each having a first transistor for clipping the voltage of each of the signal lines; a holding capacitor having a first electrode connected to a control electrode of the first transistor, and having a second electrode; a shift unit configured to supply, to the second electrodes, a plurality of voltages having values different from each other; and a voltage supplying unit provided separately from the shift unit and supplying a first voltage to the second electrodes.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: May 30, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Seiichirou Sakai, Hiroki Hiyama, Kazuo Yamazaki
  • Patent number: 9641775
    Abstract: During a period in which an electric potential of one node of a holding capacitance shifts from a first electric potential to a second electric potential, the other node of the holding capacitance is in an electrically-floating state.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: May 2, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Seiichirou Sakai, Hiroki Hiyama, Kazuo Yamazaki
  • Patent number: 9635298
    Abstract: An object of the present invention is to provide a comparator which has an input voltage range larger than the case where a conventional offset cancel technique is used, while reducing an offset voltage. A comparator circuit includes: a comparator having an inverting input terminal, a non-inverting input terminal and an output terminal; a first switch having one terminal connected to the inverting input terminal and having the other terminal connected to the output terminal; a first capacitor which has one end connected with the inverting input terminal; a first signal input terminal which is another end of the first capacitor; and a second signal input terminal which selectively inputs either one of a fixed voltage and a comparing signal into the non-inverting input terminal.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: April 25, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Kohichi Nakamura, Hideo Kobayashi, Hiroki Hiyama, Kazuo Yamazaki
  • Publication number: 20160358968
    Abstract: An apparatus according to the present invention in which a first substrate including a photoelectric conversion element and a gate electrode of a transistor, and a second substrate including a peripheral circuit portion are placed upon each other. The first substrate does not include a high-melting-metal compound layer, and the second substrate includes a high-melting-metal compound layer.
    Type: Application
    Filed: August 15, 2016
    Publication date: December 8, 2016
    Inventors: Nobuyuki Endo, Tetsuya Itano, Kazuo Yamazaki, Kyouhei Watanabe, Takeshi Ichikawa
  • Patent number: 9509931
    Abstract: A solid-state imaging apparatus, comprising a pixel array in which a plurality of pixels are arrayed, a plurality of processing units, forming a plurality of groups each including two or more processing units, an output line, a power supply line, a plurality of signal lines corresponding to the plurality of groups and connecting output nodes of the two or more processing units in the corresponding group, a plurality of connecting units provided between the output line and the plurality of signal lines, and a control unit configured to control the plurality of processing units and the plurality of connecting units based on a group including the two or more processing units being to output signals.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: November 29, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideo Kobayashi, Hiroki Hiyama, Kazuo Yamazaki, Hiroaki Kameyama
  • Publication number: 20160309101
    Abstract: Dark current from a transfer transistor is suppressed and power-supply voltage in a second semiconductor substrate is lowered. A solid-state image pickup device includes a pixel array, a plurality of common output lines receiving signals read out from a plurality of pixels, a transfer scanning unit sequentially driving the plurality of transfer transistors, a signal processing unit processing the signals output to the common signal lines, and a level shift unit making amplitude of a pulse supplied to a gate of the transfer transistor larger than amplitude of a pulse supplied to a gate of a transistor constituting the signal processing unit. The pixel array and the level shift unit are arranged on a first semiconductor substrate, whereas the plurality of common output lines and the signal processing unit are arranged on a second semiconductor substrate.
    Type: Application
    Filed: April 13, 2016
    Publication date: October 20, 2016
    Inventors: Tetsuya Itano, Kazuo Yamazaki, Nobuyuki Endo, Kyouhei Watanabe
  • Patent number: 9456161
    Abstract: An apparatus including pixels, each having first and second photoelectric conversion elements, an amplifying unit, first and second transfer gates, and a microlens, performs, in one pixel, a first operation involving turning on the first transfer gate, outputting a signal based on charge generated in the first photoelectric conversion element, turning on the first and second transfer gates while retaining the charge generated and transferred to an input node, and outputting a signal based on charges generated in the first and second photoelectric conversion elements, and, in another pixel, a second operation involving turning on the first transfer gate, not outputting a signal based on charge generated in the first photoelectric conversion element, turning on the first and second transfer gates while retaining the charge generated and transferred to the input node, and outputting a signal based on charges generated in the first and second photoelectric conversion elements.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: September 27, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Kazuo Yamazaki
  • Publication number: 20160277695
    Abstract: A solid-state imaging device includes a pixel including a photoelectric conversion element, an accumulation unit accumulating charges generated by the photoelectric conversion element, a reset unit resetting the accumulation unit at a voltage of equal to or more than 4.05 V, and an amplifier transistor amplifying and outputting a signal corresponding to amount of accumulated charges, a vertical output line connected to the pixel, a current source circuit including first to third transistors flowing a constant current through the vertical output line, and a voltage setting circuit respectively setting the gate voltages of the first to third transistors to a first voltage, a second voltage higher than the first voltage, and a third voltage higher than the second voltage and lower than the power supply voltage so as to set the drain-source voltage of each of the first to third transistors to equal to or less than 1.75 V.
    Type: Application
    Filed: February 29, 2016
    Publication date: September 22, 2016
    Inventors: Yasuhiro Oguro, Kazuo Yamazaki, Seiichirou Sakai
  • Patent number: 9443895
    Abstract: An apparatus according to the present invention in which a first substrate including a photoelectric conversion element and a gate electrode of a transistor, and a second substrate including a peripheral circuit portion are placed upon each other. The first substrate does not include a high-melting-metal compound layer, and the second substrate includes a high-melting-metal compound layer.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: September 13, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Nobuyuki Endo, Tetsuya Itano, Kazuo Yamazaki, Kyouhei Watanabe, Takeshi Ichikawa
  • Patent number: 9438841
    Abstract: A solid-state imaging apparatus includes a pixel section in which a plurality of pixels are arranged in a matrix, a column signal line configured to output a pixel signal from the pixel section, a column amplifier circuit configured to invert and amplify the pixel signal, a bypass circuit configured to bypass the column amplifier circuit, an AD converter, and a control unit configured to change an operation mode of the AD converter in accordance with the operation of the bypass circuit.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: September 6, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuo Yamazaki, Tetsuya Itano, Hiroki Hiyama
  • Publication number: 20160255248
    Abstract: An electronic circuit includes a generating circuit for generating a first group of signals and a second group of signals, and a transmission path for transmitting the first group of signals and the second group of signals. The first group of signals are composed of signals synchronized with a first edge that is one of the rising edge and the falling edge of a reference clock, and the second group of signals are composed of signals synchronized with a second edge that is the other of the rising edge and falling edge. The transmission path includes first transmission lines for transmitting the signals composing the first group and second transmission lines for transmitting the signals composing the second group, and the first and second transmission lines are alternately arranged.
    Type: Application
    Filed: February 16, 2016
    Publication date: September 1, 2016
    Inventors: Hideo Kobayashi, Kazuo Yamazaki, Hiroki Hiyama
  • Patent number: 9407847
    Abstract: Provided is a solid state imaging apparatus including: a writing memory selecting unit connected between a plurality of vertical output lines and a plurality of memories, configured to selectively store a signal transmitted from at least one of the plurality of vertical output lines into at least one of the plurality of memories; a plurality of horizontal scanning channels configured to input the signals stored in the plurality of memories; and a reading memory selecting unit connected between the plurality of memories and the plurality of horizontal scanning channels, configured to selectively output the signal stored in the at least one of the plurality of memories to at least one of the plurality of horizontal scanning channels. The reading memory selecting unit is configured to output the signals in an order corresponding to spatial arrangement of photoelectric conversion elements.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: August 2, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yu Maehashi, Hiroaki Kameyama, Hideo Kobayashi, Kazuo Yamazaki
  • Publication number: 20160209828
    Abstract: A machine tool includes a bed supported on a ground by supporting jigs, a table movable in an X-axis direction, a spindle head movable in a Y-axis direction, a quill provided to be movable in a Z-axis direction, a spindle supported by the quill to be rotatable about its axis, feed mechanisms for moving the table and the like in the axis directions, and a numerical controller controlling operation of the feed mechanisms, and the numerical controller is configured to calculate motion errors based on load values acting on the supporting jigs by a motion locus estimator, an influence coefficient storage, a motion error calculator, and a motion locus storage, generate a correction signal for compensating for the motion errors by a position corrector, and add the generated correction signals to a position control signal transmitted from a position generator to a position controller.
    Type: Application
    Filed: January 12, 2016
    Publication date: July 21, 2016
    Applicant: DMG MORI CO., LTD.
    Inventors: Hidenori Saraie, Kinji Hashimoto, Keiichiro Matsuo, Kazuo Yamazaki, Toshiya Sato