Patents by Inventor Kei Murayama

Kei Murayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060145359
    Abstract: An electronic parts packaging structure of the present invention includes a wiring substrate having a wiring pattern, a first insulating film which is formed on the wiring substrate and which has an opening portion in a packaging area where an electronic parts is mounted, the electronic parts having a connection terminal flip-chip mounted on the wiring pattern exposed in the opening portion of the first insulating film, a second insulating film for covering the electronic parts, a via hole formed in a predetermined portion of the first and second insulating films on the wiring pattern, and an upper wiring pattern formed on the second insulating film and connected to the wiring pattern through the via hole.
    Type: Application
    Filed: February 27, 2006
    Publication date: July 6, 2006
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Masahiro Sunohara, Kei Murayama, Toshinori Koyama, Kazutaka Kobayashi, Mitsutoshi Higashi
  • Publication number: 20060141676
    Abstract: To provide a method for producing a semiconductor substrate able to uniformly and quickly fill through-holes in the semiconductor substrate with conductive material. This method comprises a process for forming through-holes (14) in a substrate (10), a process for disposing solder (42) on one surface of the substrate, and a process for pressing the solder on a side of the substrate by a press (40) and heat-melting the solder to fill the through-holes in the substrate with the solder.
    Type: Application
    Filed: December 22, 2005
    Publication date: June 29, 2006
    Inventors: Kei Murayama, Mitsutoshi Higashi
  • Publication number: 20060138623
    Abstract: A stacked-type semiconductor device including a plurality of semiconductor elements stacked through a spacer is disclosed. The electrical characteristics with the bonding wires are improved and a narrow pitch is secured. The stacked-type semiconductor device includes a lower semiconductor element (2) fixed on a wiring board (1), an insulating spacer (4) fixed on the lower semiconductor element (2), a grounded spacer (10) fixed on the insulating spacer (4) and having a grounding conductor film formed on a part or the whole of the upper surface thereof, an upper semiconductor element (5) fixed on the grounded spacer (10), bonding wires (3, 6, 12) for electrically connecting between the lower semiconductor element (2) and the wiring board (1), between the upper semiconductor element (5) and the wiring board (1) and between the grounding conductor film of the grounded spacer (10) and the grounding terminal of the wiring board (1), respectively, and a seal resin (7) for sealing the bonding wires.
    Type: Application
    Filed: December 27, 2005
    Publication date: June 29, 2006
    Inventor: Kei Murayama
  • Patent number: 7067353
    Abstract: A method for manufacturing a semiconductor package, the method including the steps of attaching a bottom surface of a semiconductor wafer to a first supporting member, forming a through hole in the semiconductor wafer, separating the semiconductor wafer from the first supporting member, forming an insulating layer on at least the bottom surface of the semiconductor wafer and the inner wall of the through hole, forming a conducting layer underneath the semiconductor wafer, the conducting layer spanning at least the bottom of the through hole; and forming a conductive member in the through hole and in electrical contact with the conducting layer.
    Type: Grant
    Filed: April 16, 2004
    Date of Patent: June 27, 2006
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Naoyuki Koizumi, Kei Murayama, Takashi Kurihara, Mitsutoshi Higashi
  • Patent number: 7061261
    Abstract: A semiconductor inspection device for inspecting an electronic device is disclosed. The semiconductor inspection device includes a contact probe including a plurality of column parts disposed in continuation, each of the column parts having different height, a conductive layer formed at least on the surfaces of the column parts, a holding part for holding the contact probe, and a through-hole electrode penetrating at least one of the column parts, wherein the contact probe and the holding part are integrally formed from a single silicon substrate.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: June 13, 2006
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Kei Murayama
  • Patent number: 7057290
    Abstract: An electronic parts packaging structure of the present invention includes a wiring substrate having a wiring pattern, a first insulating film which is formed on the wiring substrate and which has an opening portion in a packaging area where an electronic parts is mounted, the electronic parts having a connection terminal flip-chip mounted on the wiring pattern exposed in the opening portion of the first insulating film, a second insulating film for covering the electronic parts, a via hole formed in a predetermined portion of the first and second insulating films on the wiring pattern, and an upper wiring pattern formed on the second insulating film and connected to the wiring pattern through the via hole.
    Type: Grant
    Filed: February 5, 2004
    Date of Patent: June 6, 2006
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masahiro Sunohara, Kei Murayama, Toshinori Koyama, Kazutaka Kobayashi, Mitsutoshi Higashi
  • Publication number: 20060073639
    Abstract: There is provided a electronic parts packaging structure that includes a mounted body on which an electronic parts is mounted, the electronic parts having a connection pad, which has an etching stopper film (a copper film, a gold film, a silver film, or a conductive past film) as an uppermost film, and mounted on the mounted body to direct the connection pad upward, an interlayer insulating film for covering the electronic parts, a via hole formed in the insulating film on the connection pad of the electronic parts, and a wiring pattern connected to the connection pad via the via hole.
    Type: Application
    Filed: November 23, 2005
    Publication date: April 6, 2006
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Masahiro Sunohara, Kei Murayama, Naohiro Mashino, Mitsutoshi Higashi
  • Publication number: 20060021791
    Abstract: An electronic component embedded substrate and a method for manufacturing the substrate are disclosed. The electronic component embedded substrate includes a substrate main body and an electronic component embedded in the substrate main body. The center plane of the electronic component in the thickness direction thereof and the center plane of the substrate main body in the thickness direction thereof generally match each other.
    Type: Application
    Filed: July 27, 2005
    Publication date: February 2, 2006
    Inventors: Masahiro Sunohara, Mitsutoshi Higashi, Kei Murayama, Hiroyuki Kato
  • Publication number: 20060018590
    Abstract: An optical waveguide mounting member for mounting to a substrate is disclosed. The optical waveguide mounting member includes an optical waveguide for transmitting optical signals therethrough and an optical waveguide mounting base material having a through-hole to which the optical waveguide is mounted. The optical waveguide mounting base material is formed of silicon.
    Type: Application
    Filed: July 20, 2005
    Publication date: January 26, 2006
    Inventor: Kei Murayama
  • Publication number: 20060013525
    Abstract: A substrate for mounting an optical element having a light emission/reception part is disclosed. The substrate includes a base material and an optical waveguide penetrating through the base material. The optical waveguide is positioned opposite to the light emission/reception part. The base material is formed of silicon.
    Type: Application
    Filed: July 14, 2005
    Publication date: January 19, 2006
    Inventor: Kei Murayama
  • Patent number: 6974721
    Abstract: In manufacturing a thin semiconductor chip, a wafer is stably held during processing to maintain a stable shape and to avoid generation of cracks on the wafer. When a thin wafer having a surface thereon is to be processed, a rigid support body is adhered to the other surface of the thin wafer and a ring-shaped frame, encircling an outer periphery of the thin wafer, is adhered to the rigid support body.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: December 13, 2005
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Naoyuki Koizumi, Kei Murayama, Shigeru Mizuno, Takashi Kurihara
  • Patent number: 6958298
    Abstract: A method for thinning a wafer by placing a wafer having a protective tape attached to the front side thereof, on which chip circuits have been fabricated, on a working table in such a manner that the protective tape is intervened between the wafer and the working table, and grinding the back side of the wafer to thin it, the method comprising, prior to the thinning by grinding, adhering the beveled portion at the front side of the wafer to the protective tape. The adhesion is preferably effected by a material exhibiting a modulus of elasticity of 0.1 to 100 MPa at the state of the adhesion of the beveled portion to the protective tape. As the material for the adhesion, an acrylic resinous material of the UV-curing type can be used.
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: October 25, 2005
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Kei Murayama
  • Publication number: 20050218502
    Abstract: In a capacitor-mounted wiring board, a plurality of wiring layers each patterned in a required shape are stacked with insulating layers interposed therebetween and are connected to each other via conductors formed to pierce the insulating layers in the direction of thickness. A decoupling capacitor is electrically connected to a wiring layer used as a power supply line or a ground line in the vicinity of the wiring layer, and mounted such that, when a current is passed through the capacitor, the direction of the current is reversed to that of the current flowing through the relevant wiring layer.
    Type: Application
    Filed: March 28, 2005
    Publication date: October 6, 2005
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Masahiro Sunohara, Kei Murayama, Mitsutoshi Higashi, Toshio Gomyo, Yukiharu Takeuchi
  • Publication number: 20050211465
    Abstract: An electronic parts packaging structure of the present invention includes a core substrate having such a structure that a recess portion is provided by forming a prepreg insulating layer having an opening portion therein on a resin layer, and an electronic parts mounted on a bottom portion of the recess portion of the core substrate such that a connection pad of the electronic parts is directed upward, and also, such a structure may be employed that the electronic parts is embedded in a resin layer of a core substrate having a structure that the resin layer is formed on the prepreg insulating layer.
    Type: Application
    Filed: March 28, 2005
    Publication date: September 29, 2005
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Masahiro Sunohara, Kei Murayama, Hiroyuki Kato, Syoji Watanabe
  • Patent number: 6943442
    Abstract: There are included a wiring substrate including a predetermined wiring pattern, an electronic parts connection terminal on an element forming surface of which is flip-chip connected to the wiring pattern, an insulating film for covering the electronic parts, a via hole formed in a predetermined portion of the electronic parts and the insulating film on the connection terminal, and an overlying wiring pattern formed on the insulating film and connected to the connection terminal via the via hole.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: September 13, 2005
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masahiro Sunohara, Kei Murayama, Naohiro Mashino, Mitsutoshi Higashi
  • Patent number: 6930392
    Abstract: There are provided the steps of forming a wiring pattern in an area except packaging area on a mounted body, the package area in which electronic parts is mounted, mounting the electronic parts in the packaging area of the mounted body to direct a surface of the electronic parts, of which a connection terminal is formed, upward, and forming an insulating film which covers the electronic parts and the wiring pattern.
    Type: Grant
    Filed: November 10, 2003
    Date of Patent: August 16, 2005
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masahiro Sunohara, Kei Murayama, Mitsutoshi Higashi
  • Publication number: 20050176169
    Abstract: To provide a method, for manufacturing a thin semiconductor chip, in which the wafer is stably held during processing to maintain a stable shape and to avoid generation of cracks on the wafer. When a thin wafer (1) having a surface (1a) thereon is to be processed, the method comprising the steps of: adhering a rigid support body (2) to the other surface (1b) of the thin wafer (1); and adhering a ring-shaped frame (3) encircling an outer periphery of the thin wafer to the rigid support body (2).
    Type: Application
    Filed: August 28, 2003
    Publication date: August 11, 2005
    Inventors: Naoyuki Koizumi, Kei Murayama, Shigeru Mizuno, Takashi Kurihara
  • Publication number: 20050156614
    Abstract: A semiconductor inspection device for inspecting an electronic device is disclosed. The semiconductor inspection device includes a contact probe including a plurality of column parts disposed in continuation, each of the column parts having different height, a conductive layer formed at least on the surfaces of the column parts, a holding part for holding the contact probe, and a through-hole electrode penetrating at least one of the column parts, wherein the contact probe and the holding part are integrally formed from a single silicon substrate.
    Type: Application
    Filed: January 14, 2005
    Publication date: July 21, 2005
    Inventor: Kei Murayama
  • Publication number: 20050110507
    Abstract: In an electrical characteristic measuring probe of the present invention constructed by assembling a plurality of probe parts, each comprising a base portion, a plurality of terminal portions extended outward from one end of the base portion, wiring patterns extended from a plurality of terminal portions onto the base portion respectively, and contact portions connected to the wiring patterns respectively, a plurality of thin plate-like probe parts are aligned such that respective thin-plate surfaces are placed in parallel with each other and the contact portions are directed in the same direction, and a plurality of probe parts and spacers are fixed by fixing means in a state that the spacer is arranged between a plurality of probe parts respectively.
    Type: Application
    Filed: November 4, 2004
    Publication date: May 26, 2005
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Naoyuki Koizumi, Akinori Shiraishi, Kei Murayama
  • Publication number: 20050098099
    Abstract: A patterning apparatus of the present invention includes a stage on which a substrate is loaded, a coating means for coating a liquid that reacts with an ultraviolet ray to deposit metal on the substrate, and an ultraviolet irradiating means for irradiating the ultraviolet ray onto the liquid that is coated on the substrate.
    Type: Application
    Filed: December 15, 2004
    Publication date: May 12, 2005
    Applicant: SHINKO ELECTRIC INDUSTRIES CO. LTD.
    Inventors: Kei Murayama, Mitsutoshi Higashi, Hideaki Sakaguchi