Abstract: A semiconductor device of an embodiment includes a first electrode; a second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode and extending in a first direction; a gate electrode surrounding the oxide semiconductor layer; and a first gate insulating layer provided between the gate electrode and the oxide semiconductor layer, the first gate insulating layer surrounding the oxide semiconductor layer, and the first gate insulating layer having a length in the first direction shorter than a length of the oxide semiconductor layer in the first direction.

Abstract: A semiconductor memory device includes a first memory cell that includes a first transistor and a first capacitor, a second transistor having a first terminal that is connected to a first terminal of the first memory cell, a first bit line that is connected to a second terminal of the first memory cell, a second bit line that is connected to a second terminal of the second transistor, and a controller that turns on the first transistor and turns off the second transistor during a write operation on the first memory cell and turns on the first transistor and the second transistor during a read operation on the first memory cell.

Abstract: A preparation method of a rubber composition for a tire assures that good processability can be obtained even if a silane coupling agent having a mercapto group is blended. The preparation method of a rubber composition for a tire is characterized by initiating kneading of a rubber component and a specific polysulfide compound before kneading the rubber component and a silane coupling agent having a mercapto group.

Abstract: A preparation method of a rubber composition for a tire assures that good processability can be obtained even if a silane coupling agent having a mercapto group is blended. The preparation method of a rubber composition for a tire is characterized by initiating kneading of a rubber component and a compound represented by the following formula (1) before kneading the rubber component and a silane coupling agent having a mercapto group. (Wherein each of R1 to R4 independently represents a straight-chain or branched chain alkyl group having 1 to 18 carbon atoms or a cycloalkyl group having 5 to 12 carbon atoms.

Abstract: According to one embodiment, a transistor includes first to third conductors, first and second oxide semiconductors, and a gate insulating film. The first and second conductors are stacked via an insulator above a substrate. The first oxide semiconductor is formed on the first conductor. The second oxide semiconductor is formed on the first oxide semiconductor. The second oxide semiconductor have a pillar shape through the second conductor along a first direction crossing a surface of the substrate. The second oxide semiconductor is different from the first oxide semiconductor. The gate insulating film is formed between the second conductor and the second oxide semiconductor. The third conductor is formed on the second oxide semiconductor.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell including a first transistor and a first capacitor, a second memory cell including a second transistor and a second capacitor, a first word line electrically coupled to the first transistor, a second word line electrically coupled to the second transistor, and a first circuit which supplies a first voltage to the first word line, and a second voltage different from the first voltage to the second word line, during a sleep mode.

Abstract: According to one embodiment, a memory includes: a bit line; a source line; a pillar extending in a first direction and including an oxide semiconductor layer; first, second and third layers arranged along the first direction and opposed to a side of the pillar; a memory cell at an intersection between the first layer and the pillar, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor at an intersection between the second layer and the pillar; and a second transistor at an intersection between the third layer and the pillar. A first end of the oxide semiconductor layer in the first direction is in contact with the source line, and a second end of the oxide semiconductor layer in the first direction is electrically disconnected from the bit line.

Abstract: According to an embodiment, a semiconductor device includes a plurality of first interconnections, a plurality of gate dielectric films, and a plurality of second interconnections. The plurality of first interconnections are oxide semiconductors formed in parallel at predetermined intervals in a first direction. The plurality of gate dielectric films are formed on surfaces of the first interconnections, respectively. The plurality of second interconnections are conductors formed at predetermined intervals in parallel to a second direction orthogonal to the first direction, respectively, to bridge over the gate dielectric films.

Abstract: According to one embodiment, a transistor includes: a gate electrode; a gate insulating layer provided on the gate electrode; an oxide semiconductor layer provided on the gate insulating layer; an oxygen supply layer provided on the oxide semiconductor layer; a first oxygen barrier layer provided on the oxygen supply layer; a source electrode provided to penetrate the oxygen supply layer and the first oxygen barrier layer and connected to the oxide semiconductor layer; and a drain electrode spaced apart from the source electrode, provided to penetrate the oxygen supply layer and the first oxygen barrier layer, and connected to the oxide semiconductor layer.

Abstract: According to an embodiment, a semiconductor device includes M write word lines, M read word lines, N write bit lines, N read bit lines, N source lines, and M×N cells. The M×N cells are arranged in a matrix including M rows×N columns. A cell in an m-th row×an n-th column includes a first FET, a second FET, and a capacitor. The first FET is connected to an m-th write word line at a gate, to an n-th write bit line at a drain, and to a source of the second FET at a source. The second FET is connected to an m-th read word line at a gate and to an n-th read bit line at a drain. The capacitor is connected to an n-th source line at one end and to the source of the first RET at the other end.

Abstract: According to one embodiment, a memory includes: a member extending in a first direction and including an oxide semiconductor layer including first to third portions arranged in order from the bit line to the source line; first, second and third conductive layers arranged along the first direction and facing the first to third portions, respectively, the first conductive layer including first material, and each of the second and third conductive layer including a second material different from the first material; a memory cell in a first position corresponding to the first portion, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor in a second position corresponding to the second portion; and a second transistor in a third position corresponding to the third portion.

Abstract: According to one embodiment, a memory includes: a first gate of a first transistor and a second gate electrode of the second transistor facing the a semiconductor layer; an oxide semiconductor layer between the first and second transistors and including first to fifth portions in order; a third gate of a first cell facing the first portion; a fourth gate of a third transistor facing the second portion; a fifth gate of a second cell facing the third portion; a sixth gate of a fourth transistor facing the fourth portion; an interconnect connected to the fifth portion; a source line connected to the first transistor; and a bit line connected to the second transistor. A material of the third gate is different from a material of the fourth gate.

Abstract: According to one embodiment, A semiconductor device includes: a first semiconductor layer; and a plurality of first transistors including a plurality of first gate structures provided on the first semiconductor layer, a first channel region provided in the first semiconductor layer and under the first gate structure, and a plurality of first diffusion regions provided in the first semiconductor layer in a manner to sandwich the first channel region.

Abstract: The rubber composition comprises 5 to 30 parts by mass of a terpene resin having a softening point of 100 to 118° C. and a molecular weight of from 500 to 10,000, and 7 to 40 parts by mass of an ?-methyl styrene resin having a molecular weight of from 700 to 3,000, based on 100 parts by mass of a rubber component comprising 60 to 95% by mass of an aromatic olefin rubber and 5 to 40% by mass of a diene olefin rubber, wherein a ratio of a content of the terpene resin to a content of the ?-methyl styrene resin (a content of the terpene resin/a content of the ?-methyl styrene resin) is from 0.2 to 5, and the tire is one having a tire member composed of the rubber composition.

Abstract: According to one embodiment, a CMOS image sensor includes a photoelectric conversion element and an amplifier transistor. The photoelectric conversion element converts incident light into an electric signal. The amplifier transistor has a heterojunction in which a Ge layer and an SiGeSn layer are joined together, as a channel region and amplifies the electric signal resulting from conversion by the photoelectric conversion element.

Abstract: A rubber composition comprises 5 to 30 parts by mass of a terpene resin having a softening point of 100 to 120° C. and a molecular weight of 500 to 10,000, and 2 to 10 parts by mass of a liquid rubber or a liquid resin having a molecular weight of 100 to 3,500, based on 100 parts by mass of a rubber component comprising 72 to 95% by mass of an aromatic olefin rubber and 5 to 28% by mass of a diene olefin rubber, wherein a ratio of a content of the terpene resin to a content of the liquid rubber or the liquid resin (a content of the terpene resin/a content of the liquid rubber or the liquid resin) is from 0.5 to 5, and the tire is one having a tire member composed of the rubber composition.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell including a transistor formed of an oxide semiconductor, an insulation film, and a control electrode, and a capacitance element configured to store a charge, the memory cell being configured to store a coupling weight of a neuron model by a charge amount accumulated in the capacitance element; and a control circuit configured to output a signal as a sum of a product between input data of the memory cell and the coupling weight.

Abstract: According to one embodiment, a memory includes: a bit line; a source line; a pillar extending in a first direction and including an oxide semiconductor layer; first, second and third layers arranged along the first direction and opposed to a side of the pillar; a memory cell at an intersection between the first layer and the pillar, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor at an intersection between the second layer and the pillar; and a second transistor at an intersection between the third layer and the pillar. A first end of the oxide semiconductor layer in the first direction is in contact with the source line, and a second end of the oxide semiconductor layer in the first direction is electrically disconnected from the bit line.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell including a first transistor and a first capacitor, a second memory cell including a second transistor and a second capacitor, a first word line electrically coupled to the first transistor, a second word line electrically coupled to the second transistor, and a first circuit which supplies a first voltage to the first word line, and a second voltage different from the first voltage to the second word line, during a sleep mode.

Abstract: According to one embodiment, a transistor includes: a gate electrode; a gate insulating layer provided on the gate electrode; an oxide semiconductor layer provided on the gate insulating layer; an oxygen supply layer provided on the oxide semiconductor layer; a first oxygen barrier layer provided on the oxygen supply layer; a source electrode provided to penetrate the oxygen supply layer and the first oxygen barrier layer and connected to the oxide semiconductor layer; and a drain electrode spaced apart from the source electrode, provided to penetrate the oxygen supply layer and the first oxygen barrier layer, and connected to the oxide semiconductor layer.