Abstract: According to one embodiment, an oxide semiconductor includes indium, gallium, and silicon. A concentration of the silicon in the oxide semiconductor is not less than 7 atomic percent and not more than 11 atomic percent.

Abstract: This semiconductor device comprises a plurality of first conductive layers arranged above a substrate in a first direction intersecting an upper surface of the substrate. The conductive layers includes a portion in which positions of ends of the first conductive layers made different from each other in a second direction intersecting the first direction. Furthermore, this semiconductor device comprises a transistor electrically connected to the portion of the conductive layers. That transistor comprises: a channel layer extending in the first direction; a gate electrode layer disposed in a periphery of the channel layer; and a gate insulating layer disposed between the channel layer and the gate electrode layer.

Abstract: An electrochemical sensor according to an embodiment, includes a first insulating film, an electrode, a semiconductor layer provided between the first insulating film and the electrode, and a charge storage layer provided between the electrode and the semiconductor layer.

Abstract: According to one embodiment, a sensing device includes a photodiode; a first transistor including a first terminal, a second terminal and a control terminal, the first terminal being connected to the photodiode; an electrode configured to detect a potential of the measurement target; a second transistor including a third terminal, a fourth terminal and a control terminal, the third terminal being connected to the electrode; and a charge storage connected to the second terminal of the first transistor and to the fourth terminal of the second transistor.

Abstract: According to one embodiment, A semiconductor device includes: a first semiconductor layer; and a plurality of first transistors including a plurality of first gate structures provided on the first semiconductor layer, a first channel region provided in the first semiconductor layer and under the first gate structure, and a plurality of first diffusion regions provided in the first semiconductor layer in a manner to sandwich the first channel region.

Abstract: A semiconductor integrated circuit according to an embodiment includes: a CMOS inverter including an n-channel transistor and a p-channel transistor, one of the n-channel transistor and the p-channel transistor being disposed above the other of the n-channel transistor and the p-channel transistor.

Abstract: This nonvolatile semiconductor memory device comprises: a memory cell array including memory cells; and a wiring line portion connecting the memory cell array to an external circuit. The memory cell array comprises a plurality of first conductive layers which are connected to the memory cells and arranged in a stacking direction. On the other hand, the wiring line portion comprises: a plurality of second conductive layers arranged in the stacking direction and respectively connected to the plurality of first conductive layers, positions of ends of the plurality of second conductive layers being different in a first direction crossing the stacking direction; a third conductive layer extending in the stacking direction from the second conductive layer; a channel semiconductor layer connected to one end of the third conductive layer; and a gate electrode wiring line disposed on a surface of the channel semiconductor layer via a gate insulating film.

Abstract: According to one embodiment, a CMOS image sensor includes a photoelectric conversion element and an amplifier transistor. The photoelectric conversion element converts incident light into an electric signal. The amplifier transistor has a heterojunction in which a Ge layer and an SiGeSn layer are joined together, as a channel region and amplifies the electric signal resulting from conversion by the photoelectric conversion element.

Abstract: According to one embodiment, a semiconductor device includes a first complementary semiconductor device provided on a semiconductor substrate, and including a CMOS circuit, a metal electrode provided above the first complementary semiconductor device, a semiconductor layer provided above the metal electrode, including an nMOS region and a pMOS region separated from each other, and containing Ge; and a second complementary semiconductor device including an nMOSFET provided on the first portion of the semiconductor layer and a pMOSFET provided on the second portion of the semiconductor layer.

Abstract: A rubber composition for a tire includes a rubber component containing at least one of a natural rubber and an epoxidized natural rubber, silica and a natural based wax, wherein the silica is contained in an amount of 10 parts by mass or more based on 100 parts by mass of the rubber component and the natural based wax is contained in an amount of 1.2% by mass or more and 2% by mass or less based on the total mass of the rubber composition for a tire, and to a tread, a side wall, a clinch and a tire using the rubber composition.

Abstract: According to one embodiment, a substrate for forming elements includes a substrate; an insulating film provided on the substrate; and a Ge layer or an SiGe layer bonded to the substrate via the insulating film. The insulating film is a laminated structure comprising a plurality of films including an oxide film, a high-dielectric constant insulating film, and a compound insulating film including a metal element and Ge.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device which includes a MISFET, includes: forming a gate insulating film on a semiconductor substrate; forming a gate electrode on the gate insulating film; implanting nitrogen equal to or more than 5.0e14 atoms/cm2 and equal to or less than 1.5e15 atoms/cm2 in the semiconductor substrate by tilted ion implantation in a direction from an outside to an inside with respect to side surfaces of the gate electrode; depositing a metal film including nickel on areas in which nitrogen atoms are implanted, the areas are in a semiconductor substrate on both sides of the gate electrode; and performing first heat processing of reacting the metal film and the semiconductor substrate and forming metal semiconductor compound layers, the shapes of the layers are controlled by the nitrogen profiles of the areas.

Abstract: According to one embodiment, a method of manufacturing a MOS semiconductor device. In the method, a gate electrode is formed on a gate insulating film provided on a channel region which is a part of an Si layer and which is interposed between a source/drain region, and a film mainly includes of Ge is made to grow on the source/drain region. Then, and the film mainly includes of Ge is made to react with a metal, forming an intermetallic compound film having a depthwise junction position identical to a growth interface of the film mainly includes of Ge.

Abstract: According to one embodiment, a semiconductor device including a tunnel FET, includes a gate electrode, which is formed on a first semiconductor layer formed of Si1?XGeX (0<x?1) through a gate insulating film, a source electrode, which is formed of a compound of a second semiconductor formed mainly using Ge and a metal, a drain electrode, which is formed of a compound of the first semiconductor layer and the metal, and a silicon (Si) thin film, which is formed between the source electrode and the first semiconductor layer. An edge portion of the source electrode and an edge portion of the drain electrode have a positional relationship of Asymmetrical to the gate electrode. The edge portion of the drain electrode is far away from an edge portion of the gate electrode toward a gate external direction compared with the edge portion of the source electrode.

Abstract: According to one embodiment, a semiconductor device having a Ge- or SiGe-fin structure includes a convex-shaped active area formed along one direction on the surface region of a Si substrate, a buffer layer of Si1-xGex (0<x<1) formed on the active area, and a fin structure of Si1-yGey (x<y?1) formed on the buffer layer. The fin structure has a side surface of a (110) plane perpendicular to the surface of the Si substrate and the width thereof in a direction perpendicular to the one direction of the fin structure is narrower than that of the buffer layer.

Abstract: According to one embodiment, a semiconductor device having a Ge— or SiGe-fin structure includes a convex-shaped active area formed along one direction on the surface region of a Si substrate, a buffer layer of Si1-xGex (0<x<1) formed on the active area, and a fin structure of Si1-yGey (x<y?1) formed on the buffer layer. The fin structure has a side surface of a (110) plane perpendicular to the surface of the Si substrate and the width thereof in a direction perpendicular to the one direction of the fin structure is narrower than that of the buffer layer.

Abstract: A field effect transistor according to an embodiment includes: a semiconductor layer; a source region and a drain region formed at a distance from each other in the semiconductor layer; a gate insulating film formed on a portion of the semiconductor layer, the portion being located between the source region and the drain region; a gate electrode formed on the gate insulating film; and a gate sidewall formed on at least one of side faces of the gate electrode, the side faces being located on a side of the source region and on a side of the drain region, the gate sidewall being made of a high dielectric material. The source region and the drain region are separately-placed from the corresponding side faces of the gate electrode.

Abstract: According to one embodiment, a semiconductor device having a Ge- or SiGe-fin structure includes a convex-shaped active area formed along one direction on the surface region of a Si substrate, a buffer layer of Si1-xGex (0<x<1) formed on the active area, and a fin structure of Si1-yGey (x<y?1) formed on the buffer layer. The fin structure has a side surface of a (110) plane perpendicular to the surface of the Si substrate and the width thereof in a direction perpendicular to the one direction of the fin structure is narrower than that of the buffer layer.

Abstract: A semiconductor device includes a gate electrode over a semiconductor substrate, a channel region provided in the semiconductor substrate below the gate electrode, and a strain generation layer configured to apply stress to the channel region, the strain generation layer being configured to apply greater stress in absolute value to the source edge of the channel region than to the drain edge of the channel region.

Abstract: According to one embodiment, a method of manufacturing a MOS semiconductor device. In the method, a gate electrode is formed on a gate insulating film provided on a channel region which is a part of an Si layer and which is interposed between a source/drain region, and a film mainly includes of Ge is made to grow on the source/drain region. Then, and the film mainly includes of Ge is made to react with a metal, forming an intermetallic compound film having a depthwise junction position identical to a growth interface of the film mainly includes of Ge.