Abstract: According to one embodiment, a non-volatile semiconductor memory device is disclosed. The device includes a semiconductor substrate, and a memory cell array provided on the semiconductor substrate. The memory cell array includes a plurality of memory transistors which are electrically rewritable and arranged in a three-dimensional manner. The device further includes a latch provided above the semiconductor substrate and configured to hold data that is to be written in the memory cell array. The latch includes a capacitor and a first field-effect transistor which is connected to the capacitor and includes a first oxide semiconductor layer.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, the cell includes a first capacitor which includes first and second electrodes, and a first transistor which includes first and second terminals and a first control terminal, the first terminal being connected to the first electrode, a first conductive line connected to the second terminal, a second conductive line connected to the second electrode, a sense amplifier, a switch element connected between the first conductive line and the sense amplifier, and a controller turning off the switch element in a write operation, applies a first potential to the first conductive line, and sets a potential of the second conductive line according to a value of write data to be written to the cell.

Abstract: According to one embodiment, a semiconductor memory includes: a first gate of a first select transistor and a second gate of a second select transistor on a gate insulating film on a semiconductor layer; an oxide semiconductor layer above the semiconductor layer; a first control gate of a first cell and a second control gate of a second cell on an insulating layer on the oxide semiconductor layer; a third gate of a first transistor between the first control gate and the second control gate; a fourth gate of a second transistor between a first end of the oxide semiconductor layer and the second control gate; an interconnect connected to the first end; a source line connected to the first select transistor; and a bit line connected to the second select transistor.

Abstract: A semiconductor integrated circuit according to an embodiment includes: a CMOS inverter including an n-channel transistor and a p-channel transistor, one of the n-channel transistor and the p-channel transistor being disposed above the other of the n-channel transistor and the p-channel transistor.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a sense amplifier, a first transfer transistor, a second transfer transistor, and a controller. The memory cell can store a first value and a second value. The sense amplifier amplifies the first value or the second value read from the memory cell to the sense node. The first transfer transistor has a first control terminal connected to the sense node. The second transfer transistor has a second control terminal connected to the sense node. The controller applies a backgate potential to backgate terminals of the first transfer transistor and the second transfer transistor.

Abstract: Provided are a rubber composition for treads which achieves a balanced improvement in fuel economy, abrasion resistance, and wet grip performance while offering good processability, and a pneumatic tire formed from the rubber composition. The present invention relates to a rubber composition for treads containing: a polybutadiene; and a terpene resin having a glass transition temperature (Tg) of 40° C. to 90° C., the polybutadiene satisfying the following conditions (A), (B) and (C): (A) a ratio (Tcp/ML1+4, 100° C.) of 5% by mass toluene solution viscosity (Tcp) to Mooney viscosity (ML1+4, 100° C.) is 0.9 to 2.3; (B) a stress relaxation time (T80) is 10.0 to 40.0 seconds, which is a time required for torque to decay by 80%, where 100% represents torque at the end of a ML1+4, 100° C. measurement; and (C) a molecular weight distribution (Mw/Mn) is 2.50 to 4.00.

Abstract: A preparation method of a rubber composition for a tire assures that good processability can be obtained even if a silane coupling agent having a mercapto group is blended. The preparation method of a rubber composition for a tire is characterized by initiating kneading of a rubber component and a specific polysulfide compound before kneading the rubber component and a silane coupling agent having a mercapto group.

Abstract: A preparation method of a rubber composition for a tire assures that good processability can be obtained even if a silane coupling agent having a mercapto group is blended. The preparation method of a rubber composition for a tire is characterized by initiating kneading of a rubber component and a compound represented by the following formula (1) before kneading the rubber component and a silane coupling agent having a mercapto group. (Wherein each of R1 to R4 independently represents a straight-chain or branched chain alkyl group having 1 to 18 carbon atoms or a cycloalkyl group having 5 to 12 carbon atoms.

Abstract: A preparation method of a rubber composition for a tire assures that good processability can be obtained even if a silane coupling agent having a mercapto group is blended. The preparation method of a rubber composition for a tire characterized by initiating kneading of a rubber component and a compound of the formula (1) before kneading the rubber component and a silane coupling agent having a mercapto group. (Wherein R1 represents a straight-chain or branched chain alkyl group having 1 to 18 carbon atoms or a cycloalkyl group having 3 to 12 carbon atoms, and R2 and R3 together with nitrogen bonded thereto form a succinimide group, a maleimide group or a phthalimide group.

Abstract: According to one embodiment, a non-volatile semiconductor memory device is disclosed. The device includes a semiconductor substrate, and a memory cell array provided on the semiconductor substrate. The memory cell array includes a plurality of memory transistors which are electrically rewritable and arranged in a three-dimensional manner. The device further includes a latch provided above the semiconductor substrate and configured to hold data that is to be written in the memory cell array. The latch includes a capacitor and a first field-effect transistor which is connected to the capacitor and includes a first oxide semiconductor layer.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a sense amplifier, a first transfer transistor, a second transfer transistor, and a controller. The memory cell can store a first value and a second value. The sense amplifier amplifies the first value or the second value read from the memory cell to the sense node. The first transfer transistor has a first control terminal connected to the sense node. The second transfer transistor has a second control terminal connected to the sense node. The controller applies a backgate potential to backgate terminals of the first transfer transistor and the second transfer transistor.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, the cell includes a first capacitor which includes first and second electrodes, and a first transistor which includes first and second terminals and a first control terminal, the first terminal being connected to the first electrode, a first conductive line connected to the second terminal, a second conductive line connected to the second electrode, a sense amplifier, a switch element connected between the first conductive line and the sense amplifier, and a controller turning off the switch element in a write operation, applies a first potential to the first conductive line, and sets a potential of the second conductive line according to a value of write data to be written to the cell.

Abstract: According to one embodiment, an oxide semiconductor includes indium, gallium, and silicon. A concentration of the silicon in the oxide semiconductor is not less than 7 atomic percent and not more than 11 atomic percent.

Abstract: This semiconductor device comprises a plurality of first conductive layers arranged above a substrate in a first direction intersecting an upper surface of the substrate. The conductive layers includes a portion in which positions of ends of the first conductive layers made different from each other in a second direction intersecting the first direction. Furthermore, this semiconductor device comprises a transistor electrically connected to the portion of the conductive layers. That transistor comprises: a channel layer extending in the first direction; a gate electrode layer disposed in a periphery of the channel layer; and a gate insulating layer disposed between the channel layer and the gate electrode layer.

Abstract: According to one embodiment, a semiconductor memory device includes a sense amplifier on a semiconductor substrate, a memory cell array including a memory cell above the sense amplifier, the memory cell including a capacitor and a first transistor, the capacitor including a first electrode and a second electrode, the first transistor including a first current path and a first control electrode controlling an on/off of the first current path, the first current path including a first terminal and a second terminal, the first terminal being electrically connected to the first electrode, and a first conductive line electrically connected to the second terminal and extending along an upper surface of the semiconductor substrate in a first direction, the first conductive line being electrically connected to the sense amplifier.

Abstract: This nonvolatile semiconductor memory device includes: a memory cell array including a memory cell; a wiring part connecting the memory cell array to an external circuit; and a transistor that connects the wiring part and the external circuit, the transistor including: a first insulating layer including a first region, a second region, and a third region, the second and third regions being disposed on both sides of the first region, and a height of an upper surface of the first region being lower than those of the second region and the third region; a semiconductor layer disposed along upper surfaces of the first region, the second region, and the third region; and a gate electrode layer disposed via the semiconductor layer and a gate insulating film, on an upper part of the second region.

Abstract: This nonvolatile semiconductor memory device includes: a memory cell array including a memory cell; a wiring part connecting the memory cell array to an external circuit; and a transistor that connects the wiring part and the external circuit, the transistor including: a first insulating layer including a first region, a second region, and a third region, the second and third regions being disposed on both sides of the first region, and a height of an upper surface of the first region being lower than those of the second region and the third region; a semiconductor layer disposed along upper surfaces of the first region, the second region, and the third region; and a gate electrode layer disposed via the semiconductor layer and a gate insulating film, on an upper part of the second region.

Abstract: According to one embodiment, a semiconductor memory device includes a sense amplifier on a semiconductor substrate, a memory cell array including a memory cell above the sense amplifier, the memory cell including a capacitor and a first transistor, the capacitor including a first electrode and a second electrode, the first transistor including a first current path and a first control electrode controlling an on/off of the first current path, the first current path including a first terminal and a second terminal, the first terminal being electrically connected to the first electrode, and a first conductive line electrically connected to the second terminal and extending along an upper surface of the semiconductor substrate in a first direction, the first conductive line being electrically connected to the sense amplifier.

Abstract: According to one embodiment, a semiconductor device includes a first complementary semiconductor device provided on a semiconductor substrate, and including a CMOS circuit, a metal electrode provided above the first complementary semiconductor device, a semiconductor layer provided above the metal electrode, including an nMOS region and a pMOS region separated from each other, and containing Ge; and a second complementary semiconductor device including an nMOSFET provided on the first portion of the semiconductor layer and a pMOSFET provided on the second portion of the semiconductor layer.

Abstract: According to one embodiment, a transistor includes a first electrode, a second electrode, a current path between the first and second electrodes, the current path including an oxide semiconductor layer, a control terminal which controls an on/off action of the current path, an insulating layer between the control terminal and the oxide semiconductor layer, a first oxide layer between the first electrode and the oxide semiconductor layer, the first oxide layer being different from the oxide semiconductor layer, and a second oxide layer between the second electrode and the oxide semiconductor layer, the second oxide layer being different from the oxide semiconductor layer.