Patents by Inventor Kentaro Mori

Kentaro Mori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140142466
    Abstract: Whether one of a user's feet has touched the ground is detected on the basis of detection values from an acceleration sensor. In a single walking cycle, a period in which the user is standing on a first (the second) foot from a time when a detecting member detects that the first (second) foot has touched the ground to a time when the detecting member detects that a second (first) foot has touched the ground is defined as a first (second) stance period. A representative value for the detection values for each of the first and the second stance period is calculated on the basis of the detection values detected by the acceleration sensor. Whether or not a walking is an ascending (descending) walking is determined on the basis of a comparison result between the calculated representative values for the first and the second stance period.
    Type: Application
    Filed: June 6, 2012
    Publication date: May 22, 2014
    Applicant: OMRON HEALTHCARE CO., LTD.
    Inventors: Yusuke Kawabe, Kentaro Mori
  • Patent number: 8710639
    Abstract: A wiring substrate in which a semiconductor element is built includes a semiconductor element; a peripheral insulating layer covering at least an outer circumferential side surface of this semiconductor element; and an upper surface-side wiring line provided on the upper surface side of the wiring substrate. The semiconductor element includes an internal terminal electrically connected to the upper surface-side wiring line on the upper surface side of the semiconductor element. This internal terminal includes a first conductive part exposed out of an insulating surface layer of the semiconductor element; an adhesion layer on this first conductive part; and a second conductive part on this adhesion layer.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: April 29, 2014
    Assignee: NEC Corporation
    Inventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Kentaro Mori, Yoshiki Nakashima
  • Patent number: 8710669
    Abstract: A semiconductor device includes a core substrate, and at least one insulating layer and at least one wiring layer that are disposed on a first surface and a second, opposite surface of the substrate. The semiconductor device includes a via disposed in the insulating layer and in the core substrate, and which connects the wiring layers to one another. The semiconductor device includes a semiconductor element mounted on the first surface, forming an electrode terminal that faces up. The semiconductor device includes a connecting portion that penetrates the insulating layer and directly connects the electrode terminal of the semiconductor element and the wiring layer on the first surface. A minimum wiring pitch of this wiring that of any wiring layer on the second surface.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: April 29, 2014
    Assignee: NEC Corporation
    Inventors: Kentaro Mori, Yoshiki Nakashima, Daisuke Ohshima, Katsumi Kikuchi, Shintaro Yamamichi
  • Patent number: 8692364
    Abstract: A semiconductor device includes an embedding layer in which one or more semiconductor element(s) is embedded and one or more interconnect layers as well as one or more insulation layers on one or both sides of the embedding layer. The embedding layer includes a woven cloth formed by reinforcement fibers. The woven cloth has an opening on its site embedding the semiconductor element. The opening is arranged so that direction of the reinforcement fibers will have a preset angle with respect to a direction of a side of or a tangent to at least a portion of the opening, the preset angle being other than a square angle or a zero angle (parallelism).
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: April 8, 2014
    Assignee: NEC Corporation
    Inventors: Katsumi Kikuchi, Yoshiki Nakashima, Kentaro Mori, Shintaro Yamamichi
  • Publication number: 20140024177
    Abstract: A semiconductor device includes: at least one semiconductor element having electrode terminals; a metal plate supporting the semiconductor element; and a wiring board covering the semiconductor element and including a plurality of insulating layers and wiring layers alternately stacked and external connection terminals on a surface, the wiring layers being electrically connected to each other by vias. The electrode terminals and the external connection terminals are electrically connected via at least one of the wiring layers and the vias. At least one of the electrode terminals, the wiring layers, and the vias is electrically connected to the metal plate.
    Type: Application
    Filed: September 23, 2013
    Publication date: January 23, 2014
    Applicant: NEC CORPORATION
    Inventors: KENTARO MORI, DAISUKE OHSHIMA, SHINTARO YAMAMICHI, HIDEYA MURAI, KATSUMI MAEDA, KATSUMI KIKUCHI, YOSHIKI NAKASHIMA
  • Ink
    Patent number: 8623939
    Abstract: An ink contains at least a first solid particle, and a second solid particle formed of a base material of a different main component from that of the first solid particle. The first solid particle and the second solid particle have zeta potentials of the same polarity, or zeta potentials of 0±5 mV. The first and second solid particles in the ink have the same surface property, specifically the same interface property in the ink. This makes it possible to use a common dispersant suited for adsorption on the first and second solid particles. In this way, more than one kind of solid particle can be stably dispersed using a sole kind of dispersant.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: January 7, 2014
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Daisuke Uematsu, Kentaro Mori, Nobuhiro Hayakawa
  • Patent number: 8608671
    Abstract: A gait change determination device includes a main body unit, an accelerometer that detects an acceleration of the main body unit, and a control unit, and determines a change in the gait of a user that wears the main body unit on a predetermined area. The control unit specifies a trajectory of a predetermined area on which the main body unit is worn during walking based on accelerations detected by the accelerometer, calculates the temporal change amount of the specified trajectory, and determines the degree of change, which is the degree of the temporal change, based on the calculated temporal change. The degree of change in the gait can be more accurately determined.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: December 17, 2013
    Assignee: Omron Healthcare Co., Ltd.
    Inventors: Shigeo Kinoshita, Kentaro Mori, Tetsuya Sato
  • Patent number: 8603310
    Abstract: A sensor control apparatus (3) includes a full-range gas sensor composed of an oxygen concentration detection cell having a pair of electrodes (21, 22) and an oxygen pump cell having a pair of electrodes (19, 20). In an electric circuit section (30), an Ip current flowing between the electrodes (19, 20) is controlled such that an electromotive force Vs produced between the electrodes (21, 22) becomes equal to a reference voltage. The reference voltage is usually set to a first reference voltage. However, when the subject gas is air, the reference voltage is set to a second reference voltage. Humidity of the subject gas is detected on the basis of an error ?Ip between an Ip current detected when the reference voltage is set to the first reference voltage, and an Ip current detected when the reference voltage is set to the second reference voltage.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: December 10, 2013
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Noboru Ishida, Kentaro Mori, Tomohiro Tajima
  • Patent number: 8569892
    Abstract: A semiconductor device includes: at least one semiconductor element having electrode terminals; a metal plate supporting the semiconductor element; and a wiring board covering the semiconductor element and including a plurality of insulating layers and wiring layers alternately stacked and external connection terminals on a surface, the wiring layers being electrically connected to each other by vias. The electrode terminals and the external connection terminals are electrically connected via at least one of the wiring layers and the vias. At least one of the electrode terminals, the is wiring layers, and the vias is electrically connected to the metal plate.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: October 29, 2013
    Assignee: NEC Corporation
    Inventors: Kentaro Mori, Daisuke Ohshima, Shintaro Yamamichi, Hideya Murai, Katsumi Maeda, Katsumi Kikuchi, Yoshiki Nakashima
  • Publication number: 20130272485
    Abstract: A nuclear reactor vessel structure includes an inner peripheral tube-shaped steel plate, an outer peripheral tube-shaped steel plate, and an intermediate tube-shaped steel plate disposed between the inner and outer peripheral tube-shaped steel plates, and is configured to support a nuclear reactor vessel on the inner peripheral side of a tube-shaped structure with concrete placed between the steel plates. The nuclear reactor vessel structure includes a support having a tube-shaped plate disposed on the inner peripheral side of the intermediate tube-shaped steel plate, and an annular plate which protrudes to the inner peripheral side of the tube-shaped plate and to which a connection section is affixed. The support is affixed to the concrete, which is placed between the inner peripheral and the intermediate tube-shaped steel plates, by first bar members, and the support is also affixed to the inner peripheral tube-shaped steel plate by second bar members.
    Type: Application
    Filed: December 6, 2011
    Publication date: October 17, 2013
    Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Hiroshi Shimizu, Ryo Fujimoto, Kentaro Mori, Hiromu Okamoto, Hisashi Sekimoto, Hiroyuki Iseki
  • Patent number: 8536691
    Abstract: A semiconductor device including a metal frame having a penetrating opening; a semiconductor chip provided in the opening; an insulating layer provided on the upper surface of the metal frame such that the insulating layer covers the upper surface, which is the circuit-formed surface of the semiconductor chip; an interconnect layer provided only on the upper-surface side of the metal frame with intervention of the insulating material and electrically connected to a circuit of the semiconductor chip; a via conductor provided on the upper surface of said semiconductor chip to electrically connect the circuit of the semiconductor chip and the interconnect layer; and a resin layer provided on the lower surface of the metal frame.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: September 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Katsumi Maeda, Takuo Funaya, Kentaro Mori, Takehiko Maeda, Masaya Kawano, Yuuji Kayashima
  • Publication number: 20130168011
    Abstract: A decorative molding film includes a base film provided with a protective layer, a coloring layer containing a polyolefin based hot melt adhesive and pigment, and an adhesive layer containing a polyolefin based hot melt adhesive, stacked in that order on one side of the base film.
    Type: Application
    Filed: August 26, 2011
    Publication date: July 4, 2013
    Applicant: TORAY INDUSTRIES, INC.
    Inventors: Kentaro Mori, Katsuhiro Minomo
  • Publication number: 20130127037
    Abstract: An object of the present invention is to provide a semiconductor device built-in substrate, which can be made thin and can suppress occurrence of warpage. The present invention provides a semiconductor substrate which is featured by including a first semiconductor device serving as a substrate, a second semiconductor device placed on the circuit surface side of the first semiconductor device in the state where the circuit surfaces of the first and second semiconductor devices are placed to face in the same direction, and an insulating layer incorporating therein the second semiconductor device, and which is featured in that a heat dissipation layer is formed at least between the first semiconductor device and the second semiconductor device, and in that the heat dissipation layer is formed on the first semiconductor device so as to extend up to the outside of the second semiconductor device.
    Type: Application
    Filed: March 3, 2011
    Publication date: May 23, 2013
    Applicant: NEC CORPORATION
    Inventors: Kentaro Mori, Shintaro Yamamichi, Katsumi Kikuchi, Daisuke Ohshima, Yoshiki Nakashima, Hideya Murai
  • Publication number: 20130123669
    Abstract: A gait change determination device includes a main body unit, an accelerometer that detects an acceleration of the main body unit, and a control unit, and determines a change in the gait of a user that wears the main body unit on a predetermined area. The control unit specifies a trajectory of a predetermined area on which the main body unit is worn during walking based on accelerations detected by the accelerometer, calculates the temporal change amount of the specified trajectory, and determines the degree of change, which is the degree of the temporal change, based on the calculated temporal change. The degree of change in the gait can be more accurately determined.
    Type: Application
    Filed: July 19, 2011
    Publication date: May 16, 2013
    Applicant: OMRON HEALTHCARE CO LTD
    Inventors: Shigeo Kinoshita, Kentaro Mori, Tetsuya Sato
  • Patent number: 8427374
    Abstract: To provide an inexpensive planar antenna of stable quality which has a circuit with low resistance and in which electrical continuity between the antenna and the electronic part such as IC chip is secured, a planar antenna is made to have a circuit pattern comprised of an antenna part and a connecting terminal part on a resin film, wherein the circuit pattern has a metal layer, a conductive layer provided on the top surface of the connecting terminal part of the metal layer, and a protective layer provided on the top surface of the antenna part of the metal layer and on the section from the side surface to a portion of the top surface of the conductive layer.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: April 23, 2013
    Assignee: Toray Industries, Inc.
    Inventors: Kentaro Mori, Kiyohiko Itoh
  • Publication number: 20130088841
    Abstract: The present invention has an object to provide a substrate with a built-in functional element, including the functional element above a metal plate, in which crosstalk noise between signal wirings can be reduced and higher characteristic impedance matching can be achieved. An aspect of the present invention provides a substrate with a built-in functional element, including: a metal plate that includes a concave portion and serves as a ground; the functional element that is placed in the concave portion and includes an electrode terminal; a first insulating layer that covers the functional element and is placed in contact with the metal plate; a first wiring layer including first signal wiring that is opposite the metal plate with the first insulating layer being interposed therebetween; a second insulating layer that covers the first wiring layer; and a ground layer formed of a ground plane that is opposite the first wiring layer with the second insulating layer being interposed therebetween.
    Type: Application
    Filed: January 19, 2011
    Publication date: April 11, 2013
    Applicant: NEC Corporation
    Inventors: Daisuke Ohshima, Kentaro Mori, Yoshiki Nakashima, Katsumi Kikuchi, Shintaro Yamamichi
  • Patent number: 8389414
    Abstract: A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: March 5, 2013
    Assignees: NEC Corporation, Renesas Electronics Corporation
    Inventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Kentaro Mori, Takehiko Maeda, Hirokazu Honda, Kenta Ogawa, Jun Tsukano
  • Publication number: 20130050967
    Abstract: An object of the present invention is to provide a functional device-embedded substrate that can be thinned and suppress occurrence of warpage. The present invention provides a functional device-embedded substrate including at least a functional device including an electrode terminal, and a covering insulating layer covering at least an electrode terminal surface and a side surface of the functional device, the functional device-embedded substrate including a first pillar structure around the functional device inside the covering insulating layer, the first pillar structure including a material having a thermal expansion coefficient between thermal expansion coefficients of the functional device and the covering insulating layer, wherein the first pillar structure is arranged at a position where a shortest distance from a side surface of the functional device to a side surface of the first pillar structure is smaller than a thickness of the functional device.
    Type: Application
    Filed: January 19, 2011
    Publication date: February 28, 2013
    Applicant: NEC CORPORATION
    Inventors: Daisuke Ohshima, Katsumi Kikuchi, Yoshiki Nakashima, Kentaro Mori, Shintaro Yamamichi
  • Publication number: 20130032480
    Abstract: A gas sensor (100) includes an oxygen pump cell (135) and an oxygen-concentration detection cell (150) laminated together with a spacer (145) interposed therebetween. The spacer (145) has a gas detection chamber (145c) which faces electrodes (137, 152) of the cells (135, 150). The oxygen-concentration detection cell (150) produces an output voltage corresponding to the concentration of oxygen in the gas detection chamber (145c). The oxygen pump cell (135) pumps oxygen into and out of the measurement chamber (145c) such that the output voltage of the oxygen-concentration detection cell (150) becomes equal to a predetermined target voltage. A leakage portion mainly formed of zirconia is disposed between which electrically connects the oxygen-concentration detection cell (150) and the oxygen pump cell (135).
    Type: Application
    Filed: August 2, 2012
    Publication date: February 7, 2013
    Applicant: NGK SPARK PLUG CO., LTD.
    Inventors: Tetsuya ITO, Satoshi TERAMOTO, Kentaro MORI
  • Publication number: 20130026632
    Abstract: A wiring substrate in which a semiconductor element is built includes a semiconductor element; a peripheral insulating layer covering at least an outer circumferential side surface of this semiconductor element; and an upper surface-side wiring line provided on the upper surface side of the wiring substrate. The semiconductor element includes an internal terminal electrically connected to the upper surface-side wiring line on the upper surface side of the semiconductor element. This internal terminal includes a first conductive part exposed out of an insulating surface layer of the semiconductor element; an adhesion layer on this first conductive part; and a second conductive part on this adhesion layer.
    Type: Application
    Filed: February 22, 2011
    Publication date: January 31, 2013
    Applicant: NEC CORPORATION
    Inventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Kentaro Mori, Yoshiki Nakashima