Patents by Inventor Kentaro Mori

Kentaro Mori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150179623
    Abstract: To provide a semiconductor device having improved reliability. A semiconductor chip is conveyed onto a chip mounting region of a wiring board by means of a bonding jig to electrically couple the semiconductor chip and the wiring board to each other. The bonding jig for mounting the semiconductor chip on the wiring board is equipped with a retention portion for adsorbing and retaining a logic chip, a pressing portion for pressing against the back surface of the semiconductor chip, and a sealing portion to be firmly attached to the peripheral edge portion of the back surface of the semiconductor chip. The surface of the sealing portion to be firmly attached to the back surface of the semiconductor chip is made of a resin.
    Type: Application
    Filed: December 11, 2014
    Publication date: June 25, 2015
    Inventors: Yoshihiro ONO, Shinji WATANABE, Tsuyoshi KIDA, Kentaro MORI, Kenji SAKATA, Yusuke YAMADA
  • Publication number: 20150179615
    Abstract: To improve reliability of a semiconductor device. In a conductive material that electrically couples a Cu pillar electrode and a lead, an alloy part comprised of an alloy of tin and copper is formed inside this conductive material. At this time, the alloy part contacts both the Cu pillar electrode and the lead, and the Cu pillar electrode and the lead are bound through the alloy part. Similarly, also in FIG. 8, it is found that the Cu pillar electrode and the lead are electrically coupled to each other by the alloy part. Thereby, it is possible to improve electric coupling reliability between the Cu pillar electrode and the lead.
    Type: Application
    Filed: December 2, 2014
    Publication date: June 25, 2015
    Inventors: Shinji WATANABE, Tsuyoshi KIDA, Yoshihiro ONO, Kentaro MORI, Kenji SAKATA, Yusuke YAMADA
  • Publication number: 20150171066
    Abstract: This invention is to improve performance of a semiconductor integrated circuit device. A semiconductor device has a peripheral circuit chip and a logic chip mounted over a wiring substrate. The wiring substrate and the peripheral circuit chip are electrically connected, and the peripheral circuit chip and the logic chip are electrically connected. The peripheral circuit chip includes a first peripheral circuit, a power supply controller, a temperature sensor and a first RAM. The logic chip includes a CPU, a second peripheral circuit and a second RAM. The first peripheral circuit and the first RAM are manufactured based on a first process rule. The CPU, the second peripheral circuit and the second RAM are manufactured based on a second process rule finer than the first process rule.
    Type: Application
    Filed: December 18, 2014
    Publication date: June 18, 2015
    Inventors: Shintaro YAMAMICHI, Atsushi NAKAMURA, Masayuki ITO, Naoto TAOKA, Kentaro MORI
  • Patent number: 9052279
    Abstract: When a detection signal obtained from the cell of a gas sensor (S15) has reached a start determination value (specifically, when the output voltage of the cell is higher than 600 mV (S16: YES) or lower than 300 mV (S17: YES)), a pulse voltage is applied to the cell (S18), and a start-time internal resistance is obtained on the basis of the detection signal having changed as a result of application of the pulse voltage (S20). The start-time internal resistance is compared with a deterioration determination value set in advance (S21). A target resistance of the cell used in temperature control (energization control) for the heater is corrected in accordance with the result of the comparison (S28). Thus, the temperature of the cell can be stably maintained constant irrespective of deterioration of the cell.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: June 9, 2015
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventors: Tsuyoshi Kato, Kentaro Mori, Soichi Kawaguchi, Yoshinori Hibino, Ryosuke Ichida
  • Publication number: 20150129120
    Abstract: A film for decorative forming includes a layered structure in which a protective layer and a colored layer are arranged sequentially in this order on a base material film, wherein, when a storage elastic modulus of the protective layer at 100° C. is written as E?a(100) and a storage elastic modulus of the colored layer at 100° C. is written as E?b(100), E?a(100) and E?b(100) satisfy conditions (1) to (3): (1) E?a(100)/E?b(100) is less than or equal to 8, (2) E?a(100) is greater than or equal to 10 MPa, (3) E?b(100) is less than or equal to 12 MPa.
    Type: Application
    Filed: May 28, 2013
    Publication date: May 14, 2015
    Inventors: Katsuhiro Minomo, Kentaro Mori
  • Patent number: 9027912
    Abstract: A vibration damping device including: an inner shaft member; a main rubber elastic body fixed to an outer circumference surface of the inner shaft member; and an outer bracket attached to an outer circumference surface of the main rubber elastic body. At least one locking projection formed to an inner circumference surface on a bracket main unit provided to the outer bracket is inserted and locked in a circumference direction in at least one locking groove formed on the outer circumference surface of the main rubber elastic body. The main rubber elastic body is held between axially opposed surfaces of an abutting protruding part formed on one axial end of the bracket main unit and a retaining protruding part formed on a press fit metal fitting press fit and fixed to another axial end of the bracket main unit.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: May 12, 2015
    Assignees: Tokai Rubber Industries, Ltd., Toyota Jidosha Kabushiki Kaisha
    Inventors: Satoru Hibi, Akio Saiki, Takayoshi Yasuda, Masahiro Ohnishi, Kentaro Mori, Nobuya Yoshida, Hiroshi Miya
  • Patent number: 8975150
    Abstract: A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: March 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Kentaro Mori, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Masaya Kawano, Takehiko Maeda, Kouji Soejima
  • Publication number: 20150053474
    Abstract: An object of the present invention is to propose a functional element built-in substrate which enables an electrode terminal of a functional element to be well connected to the back surface on the side opposite to the electrode terminal of the functional element, and which can be miniaturized.
    Type: Application
    Filed: November 4, 2014
    Publication date: February 26, 2015
    Applicant: NEC CORPORATION
    Inventors: Yoshiki NAKASHIMA, Shintaro YAMAMICHI, Katsumi KIKUCHI, Kentaro MORI, Hideya MURAI
  • Patent number: 8959988
    Abstract: In an oxygen sensor control apparatus, a CPU obtains a correction coefficient for calibrating the relation between output value of an oxygen sensor and oxygen concentration when a fuel cut operation is performed. When the amount of scavenging air (total supply amount of air) becomes equal to or greater than a predetermined amount in each fuel cut period, the CPU calculates an average output value Ipav from a plurality of output values (concentration corresponding values) Ipr of the oxygen sensor, from which values deviating from a predetermined range R1 have been removed. Subsequently, the CPU averages the values obtained in a plurality of fuel cut periods to thereby obtain a plural-time average output value Ipavf. The CPU obtains a correction coefficient for correcting the actual output value Ip of the oxygen sensor 20 on the basis of the Ipavf value and a previously set reference output value.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: February 24, 2015
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Hiroshi Inagaki, Kentaro Mori
  • Publication number: 20150027614
    Abstract: A decorative molding film has a laminated structure in which a coloring layer, protective layer and a base film are stacked in that order or in which the base film is disposed between the coloring layer and the protective layer, wherein the rupture elongation of said base film and the protective layer at 120° C. is 200% or more, wherein the coloring layer includes at least a binder resin, and a glittering material with an average longer diameter of from 5 to 12 ?m, and wherein the stress at 100% elongation of the coloring layer at 120° C. is 4 MPa or less; which decorative molding film has less occurrence of surface irregularity at a highly stretched region.
    Type: Application
    Filed: January 18, 2013
    Publication date: January 29, 2015
    Inventors: Kentaro Mori, Katsuhiro Minomo
  • Patent number: 8929090
    Abstract: An object of the present invention is to propose a functional element built-in substrate which enables an electrode terminal of a functional element to be well connected to the back surface on the side opposite to the electrode terminal of the functional element, and which can be miniaturized.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: January 6, 2015
    Assignee: NEC Corporation
    Inventors: Yoshiki Nakashima, Shintaro Yamamichi, Katsumi Kikuchi, Kentaro Mori, Hideya Murai
  • Publication number: 20140367546
    Abstract: A vibration damping device including: an inner shaft member; a main rubber elastic body fixed to an outer circumference surface of the inner shaft member; and an outer bracket attached to an outer circumference surface of the main rubber elastic body. At least one locking projection formed to an inner circumference surface on a bracket main unit provided to the outer bracket is inserted and locked in a circumference direction in at least one locking groove formed on the outer circumference surface of the main rubber elastic body. The main rubber elastic body is held between axially opposed surfaces of an abutting protruding part formed on one axial end of the bracket main unit and a retaining protruding part formed on a press fit metal fitting press fit and fixed to another axial end of the bracket main unit.
    Type: Application
    Filed: April 14, 2014
    Publication date: December 18, 2014
    Applicants: TOKAI RUBBER INDUSTRIES, LTD., TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Satoru HIBI, Akio SAIKI, Takayoshi YASUDA, Masahiro OHNISHI, Kentaro MORI, Nobuya YOSHIDA, Hiroshi MIYA
  • Publication number: 20140367863
    Abstract: A semiconductor device comprises: a semiconductor element; a support substrate arranged on a surface of the semiconductor element opposite to a surface thereof provided with a pad, the support substrate being wider in area than the semiconductor element; a burying insulating layer on the support substrate for burying the semiconductor element therein; a fan-out interconnection led out from the pad to an area on the burying insulating layer lying more peripherally outwardly than the semiconductor element; and a reinforcement portion arranged in a preset area on top of outer periphery of the semiconductor element for augmenting the mechanical strength of the burying insulating layer and the fan-out interconnection.
    Type: Application
    Filed: August 26, 2014
    Publication date: December 18, 2014
    Applicant: NEC CORPORATION
    Inventors: SHINTARO YAMAMICHI, KENTARO MORI, HIDEYA MURAI
  • Patent number: 8872334
    Abstract: In a manufacturing method of a semiconductor device incorporating a semiconductor element in a multilayered wiring structure including a plurality of wiring layers and insulating layers, a semiconductor element is mounted on a silicon support body whose thickness is reduced to a desired thickness and which are equipped with a plurality of through-vias running through in the thickness direction; an insulating layer is formed to embed the semiconductor element; then, a plurality of wiring layers is formed on the opposite surfaces of the silicon support body in connection with the semiconductor element. Thus, it is possible to reduce warping which occurs in proximity to the semiconductor element in manufacturing, thus improving a warping profile in the entirety of a semiconductor device. Additionally, it is possible to prevent semiconductor elements from becoming useless, improve a yield rate, and produce a thin-type semiconductor device with high-density packaging property.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: October 28, 2014
    Assignee: NEC Corporation
    Inventors: Shintaro Yamamichi, Katsumi Kikuchi, Yoshiki Nakashima, Kentaro Mori
  • Publication number: 20140295181
    Abstract: A multilayer film includes a protective layer, a color layer and an adhesive layer, with a molding film disposed between either of the adjoining pairs of layers or on an opposite surface of the protective layer to the color layer, wherein the protective layer contains a polyurethane resin (U) formed at least from an active hydrogen component (A) and an organic isocyanate component (B) and having a polycarbonate skeleton with an alicyclic hydrocarbon group and that conditions (1) and/or (2) are satisfied: (1): The polyurethane resin (U) is a polyurethane resin (U1) having an alkoxysilyl and/or a silanol group in a molecule, (2): The protective layer contains a compound (X) having a glycidyl ether, and an alkoxysilyl and/or a silanol group, and the polyurethane resin (U) is a polyurethane resin (U2) that has an amino group, or a carboxyl group and/or a salt thereof.
    Type: Application
    Filed: December 25, 2012
    Publication date: October 2, 2014
    Applicants: Toray Industries, Inc., Sanyo Chemical Industries, Ltd.
    Inventors: Katsuhiro Minomo, Kentaro Mori, Yosuke Matsui
  • Patent number: 8833923
    Abstract: There is provided a method for forming a conductor, including a first printing step of printing a contour part of the conductor with a first printing ink, a drying step of drying the printed contour part, and a second printing step of printing a remaining part of the conductor with a second printing ink, wherein the second printing ink contains a conductive material and has a surface tension lower than or equal to a surface tension of the first printing ink.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: September 16, 2014
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Kentaro Mori, Daisuke Uematsu, Nobuhiro Hayakawa
  • Patent number: 8827435
    Abstract: There is provided an ink for printing a conductor pattern on a substrate, including platinum particles, wherein 70% or more of the platinum particles have a particle size of 0.05 to 0.5 ?m. Even when the viscosity of the printing ink is controlled to a relatively low level for use in ink-jet printing process, it is possible by such particle size distribution control to prevent sedimentation of the platinum particles and excessive shrinkage of the conductor pattern due to sintering of the platinum particles during firing so that the conductor pattern can attain improved conduction characteristics.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: September 9, 2014
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Daisuke Uematsu, Kentaro Mori, Nobuhiro Hayakawa
  • Patent number: 8810008
    Abstract: A semiconductor element-embedded substrate includes a semiconductor element; a chip component; a peripheral insulating layer covering at least the outer circumferential side surfaces thereof; an upper surface-side wiring line provided on the upper surface side of the substrate; and a lower surface-side wiring line provided on the lower surface side of the substrate. The built-in semiconductor element includes a terminal on the upper surface side thereof, and this terminal is electrically connected to the upper surface-side wiring line. The built-in chip component includes an upper surface-side terminal electrically connected to the upper surface-side wiring line; a lower surface-side terminal electrically connected to the lower surface-side wiring line; and a through-chip via penetrating through the chip component to connect the upper surface-side terminal and the lower surface-side terminal.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: August 19, 2014
    Assignee: NEC Corporation
    Inventors: Kentaro Mori, Shintaro Yamamichi, Hideya Murai, Katsumi Kikuchi, Yoshiki Nakashima, Daisuke Ohshima
  • Patent number: 8771488
    Abstract: A gas sensor (100) includes an oxygen pump cell (135) and an oxygen-concentration detection cell (150) laminated together with a spacer (145) interposed therebetween. The spacer (145) has a gas detection chamber (145c) which faces electrodes (137, 152) of the cells (135, 150). The oxygen-concentration detection cell (150) produces an output voltage corresponding to the concentration of oxygen in the gas detection chamber (145c). The oxygen pump cell (135) pumps oxygen into and out of the measurement chamber (145c) such that the output voltage of the oxygen-concentration detection cell (150) becomes equal to a predetermined target voltage. A leakage portion mainly formed of zirconia is disposed between which electrically connects the oxygen-concentration detection cell (150) and the oxygen pump cell (135).
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: July 8, 2014
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Tetsuya Ito, Satoshi Teramoto, Kentaro Mori
  • Patent number: 8766440
    Abstract: A wiring board including a built-in semiconductor element includes the semiconductor element, a peripheral insulating layer covering an outer peripheral side surface of the semiconductor element, an upper surface-side wiring provided on an upper surface side of the wiring board, and a lower surface-side wiring provided on a lower surface side of the wiring board. The semiconductor element includes a first wiring structure layer including a first wiring and a first insulating layer alternately provided on a semiconductor substrate, and a second wiring structure layer including a second wiring and a second insulating layer alternately provided on the first wiring structure layer. The upper surface-side wiring includes a wiring electrically connected to the first wiring via the second wiring. The second wiring is thicker than the first wiring and thinner than the upper surface-side wiring. The second insulating layer is formed of a resin material and is thicker than the first insulating layer.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: July 1, 2014
    Assignee: NEC Corporation
    Inventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Kentaro Mori, Yoshiki Nakashima, Daisuke Ohshima