Abstract: A semiconductor device comprises: a core substrate; at least one insulating layer and at least one wiring layer which are disposed on each of a first surface of the core substrate and a second surface opposite to the first surface; a via(s) which is disposed in each of the insulating layer and the core substrate, and connects the wiring layers to each other; a semiconductor element, mounted on the first surface of the core substrate, with a surface for forming an electrode terminal(s) facing up; and a connecting portion(s) which penetrates the insulating layer disposed on the first surface and directly connects the electrode terminal of the semiconductor element and the wiring layer disposed on the first surface. A minimum wiring pitch of the wiring layer directly connected to the connecting portion is smaller than that of any of the wiring layer(s) disposed on the second surface.

Abstract: A gas sensor including: a gas sensing element including first and second ceramic layers. The first ceramic layer has a first through hole and a first through hole conductor covering an inner surface thereof. The first ceramic layer includes a first conductor which includes: a first peripheral conductive portion electrically connected to the first through hole conductor; a first lead portion that is narrower than the first peripheral conductive portion; and a first contact conductive portion that is wider than the first lead portion. The first peripheral conductive portion, the first lead portion and the first contact conductive portion are integrally formed and arranged in this order in a longitudinal direction. The second ceramic layer includes a second conductor electrically connected to at least the first contact conductive portion.

Abstract: A gas sensor element for detecting a specific gas component contained in a gas to be measured includes: a solid electrolyte layer; a first electrode disposed on the solid electrolyte layer; a second electrode disposed on the solid electrolyte layer; and a porous layer disposed on one of the first electrode and the second electrode such that the gas to be measured is introduced from the outside of said gas sensor element and passes through the porous layer to at least one of the first electrode and the second electrode. The porous layer includes: a first porous layer including a first ceramic porous body which does not include noble metal particles dispersed therein; and a second porous layer provided on the first porous layer and including a second ceramic porous body and noble metal particles dispersed therein.

Abstract: A sensor control apparatus (3) includes a full-range gas sensor composed of an oxygen concentration detection cell having a pair of electrodes (21, 22) and an oxygen pump cell having a pair of electrodes (19, 20). In an electric circuit section (30), an Ip current flowing between the electrodes (19, 20) is controlled such that an electromotive force Vs produced between the electrodes (21, 22) becomes equal to a reference voltage. The reference voltage is usually set to a first reference voltage. However, when the subject gas is air, the reference voltage is set to a second reference voltage. Humidity of the subject gas is detected on the basis of an error ?Ip between an Ip current detected when the reference voltage is set to the first reference voltage, and an Ip current detected when the reference voltage is set to the second reference voltage.

Abstract: A nebulizer includes a main body unit, an atomization unit, and a breath detection unit, which is a function unit for realizing an additional function of the nebulizer. The main body unit and the atomization unit are separable. The atomization unit includes a storage section for storing the medicinal solution, and an atomizing section for spraying the medicinal solution by atomizing the medicinal solution in the storage section. The main body unit includes a control circuit for performing control to operate the atomizing section. The breath detection unit is attachable between the main body unit and the atomization unit.

Abstract: A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.

Abstract: A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.

Abstract: A planar antenna has a circuit pattern including an antenna part and a connection terminal part on a plastic film, in which the circuit pattern has a metal layer and a heat-sealable conductive layer provided on a surface layer of a connection terminal part of the metal layer. The planar antenna is obtained by forming a circuit pattern including a metal layer on a plastic film, providing a heat-sealable conductive layer in a connection terminal part of the circuit pattern, and then removing an unnecessary part with etching.

Abstract: In order to compensate for variation in output of sensor elements 10, there is provided a compensating resistor 220 that has a resistance value reflected by correction information. The resistor 220 is connected in parallel with a VS cell 245 through paired electrode leads 236 and 237 and paired electrode pads 232 and 233. The paired electrode leads 236 and 237 are placed at a position electrically isolated from solid electrolyte substrates 120 and 140.

Abstract: In a wiring substrate containing a semiconductor element, the wiring substrate includes a supporting substrate; a semiconductor element provided on the supporting substrate; a peripheral insulating layer covering at least an outer circumferential side surface of the semiconductor element; and upper surface-side wiring provided on the upper surface side of the wiring substrate. The semiconductor element includes a semiconductor substrate; a first wiring-structure layer including first wiring and a first insulating layer alternately formed on the semiconductor substrate; and a second wiring-structure layer including second wiring and a second insulating layer alternately formed on the first wiring-structure layer. The upper surface-side wiring includes fan-out wiring led out from immediately above the semiconductor element to a peripheral region external to an outer edge of the semiconductor element. The fan-out wiring is electrically connected to the first wiring through the second wiring.

Abstract: A semiconductor device, in which a semiconductor element is mounted on one side of a circuit board that is made up from an insulating layer and a wiring layer, includes metal posts provided on the side of the circuit board on which the semiconductor element is mounted; and a sealing layer provided on the side of the circuit board on which the semiconductor element is mounted such that the semiconductor element is covered and such that only portions of the metal posts are exposed.

Abstract: Semiconductor device has a semiconductor chip embedded in an insulating layer. A semiconductor device comprises a semiconductor chip formed to have external connection pads and a positioning mark that is for via formation; an insulating layer containing a non-photosensitive resin as an ingredient and having a plurality of vias; and wiring electrically connected to the external connection pads through the vias and at least a portion of which is formed on the insulating layer. The insulating layer is formed to have a recess in a portion above the positioning mark. The bottom of the recess is the insulating layer alone. Vias have high positional accuracy relative to the mark.

Abstract: A semiconductor device includes: at least one semiconductor element having electrode terminals; a metal plate supporting the semiconductor element; and a wiring board covering the semiconductor element and including a plurality of insulating layers and wiring layers alternately stacked and external connection terminals on a surface, the wiring layers being electrically connected to each other by vias. The electrode terminals and the external connection terminals are electrically connected via at least one of the wiring layers and the vias. At least one of the electrode terminals, the is wiring layers, and the vias is electrically connected to the metal plate.

Abstract: A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.

Abstract: A semiconductor device includes a plural number of interconnects and a plural number of vias are stacked. A semiconductor element is enclosed in an insulation layer. At least one of the vias provided in insulation layers and/or at least one of interconnects provided in the interconnect layers are of cross-sectional shapes different from those of the vias formed in another one of the insulation layers and/or interconnects provided in another one of the interconnect layers.

Abstract: A gas sensor having a sensor element including: a plate-shaped solid electrolyte body; and a pair of electrodes sandwiching the electrolyte body. The electrodes include a measurement electrode portion, and a standard electrode portion disposed in an inner portion of the sensor element. A lead portion, which extends along the surface of the solid electrolyte body, is connected to the standard electrode portion. The standard electrode portion is mainly formed with a precious metal and contains a ceramic. The lead portion is mainly formed of a precious metal and has a ceramic content smaller than the standard electrode portion. A porous portion, which extends to the inner portion of the sensor element along the surface of the solid electrolyte body, has a gas permeability higher than the lead portion, is mainly formed with a ceramic, and is connected to the standard electrode portion.

Abstract: A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.

Abstract: A nebulizer includes a nebulizer body and a relay pipe. The nebulizer body includes a connection portion that has an aerosol lead-out port to lead out aerosol, and the relay pipe includes a connection portion that has an aerosol introduction port to introduce the aerosol. The nebulizer body and the relay pipe can take a first connection state in which the relay pipe is detachably connected to the nebulizer body and a second connection state in which the relay pipe is connected to the nebulizer body so as to be not able to be detached from the nebulizer body. In the first connection state, the aerosol introduction port and the aerosol lead-out port are communicated with each other. In the second connection state, the aerosol lead-out port is blocked by a blocking portion provided in the relay pipe. Therefore, the nebulizer in which reuse of the nebulizer body or relay pipe is simply prohibited after the usage can be provided by the configuration.

Abstract: In forming a semiconductor device, an insulation layer is formed on top of a semiconductor chip having a plurality of external terminals. A plurality of interconnections is formed on the insulating layer. External terminals are electrically connected to coordinated interconnections through a plurality of vias formed in the insulation layer. The interconnections are each formed integral with a via conduction part which covers the entire surfaces of the bottom and the sidewall sections of the via. The interconnection is formed so as to be narrower in its region overlying the via than the upper via diameter.

Abstract: To provide an inexpensive planar antenna of stable quality which has a circuit with low resistance and in which electrical continuity between the antenna and the electronic part such as IC chip is secured, a planar antenna is made to have a circuit pattern comprised of an antenna part and a connecting terminal part on a resin film, wherein the circuit pattern has a metal layer, a conductive layer provided on the top surface of the connecting terminal part of the metal layer, and a protective layer provided on the top surface of the antenna part of the metal layer and on the section from the side surface to a portion of the top surface of the conductive layer.