Patents by Inventor Kevin G. Duesman
Kevin G. Duesman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190148314Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements, and a plated pad electrically coupling at least a part of the first contact pad to at least a part of the second contact pad. The substrate includes a substrate contact electrically coupled to the plated pad on the die.Type: ApplicationFiled: September 21, 2018Publication date: May 16, 2019Inventors: James E. Davis, Kevin G. Duesman, Jeffrey P. Wright, Warren L. Boyer
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Publication number: 20190148359Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to both the first and second contact pads. The semiconductor device assembly can further include a second die including a third contact pad electrically coupled to a third circuit on the second die including at least a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad and electrically disconnected from the fourth contact pad.Type: ApplicationFiled: November 27, 2018Publication date: May 16, 2019Inventors: James E. Davis, John B. Pusey, Zhiping Yin, Kevin G. Duesman
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Patent number: 10283462Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements, and a plated pad electrically coupling at least a part of the first contact pad to at least a part of the second contact pad. The substrate includes a substrate contact electrically coupled to the plated pad on the die.Type: GrantFiled: November 13, 2017Date of Patent: May 7, 2019Assignee: Micron Technology, Inc.Inventors: James E. Davis, Kevin G. Duesman, Jeffrey P. Wright, Warren L. Boyer
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Publication number: 20180366453Abstract: In one embodiment, an apparatus comprises a tier comprising alternating first and second layers, wherein the first layers comprise a first conductive material and the second layers comprise a first dielectric material; a lower metal layer below the tier; a bond pad above the tier, the bond pad coupled to the lower metal layer by a via extending through the tier; and a first channel formed through a portion of the tier, the first channel surrounding the via, the first channel comprising a second dielectric material.Type: ApplicationFiled: June 16, 2017Publication date: December 20, 2018Applicant: Intel CorporationInventors: Merri Lyn Carlson, Hongbin Zhu, Gordon A. Haller, James E. Davis, Kevin G. Duesman, James Mathew, Michael P. Violette
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Patent number: 10128229Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to both the first and second contact pads. The semiconductor device assembly can further include a second die including a third contact pad electrically coupled to a third circuit on the second die including at least a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad and electrically disconnected from the fourth contact pad.Type: GrantFiled: November 13, 2017Date of Patent: November 13, 2018Assignee: Micron Technology, Inc.Inventors: James E. Davis, John B. Pusey, Zhiping Yin, Kevin G. Duesman
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Patent number: 8541836Abstract: Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.Type: GrantFiled: November 12, 2012Date of Patent: September 24, 2013Assignee: Micron Technology, Inc.Inventors: Kurt D. Beigel, Jigish D. Trivedi, Kevin G. Duesman
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Patent number: 8431980Abstract: A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.Type: GrantFiled: July 12, 2010Date of Patent: April 30, 2013Assignee: Micron Technology, Inc.Inventors: Thomas W. Voshell, Lucien J. Bissey, Kevin G. Duesman
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Patent number: 8319280Abstract: Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.Type: GrantFiled: September 13, 2011Date of Patent: November 27, 2012Assignee: Micron Technology, Inc.Inventors: Kurt D. Beigel, Jigish D. Trivedi, Kevin G. Duesman
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Publication number: 20120001245Abstract: Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.Type: ApplicationFiled: September 13, 2011Publication date: January 5, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Kurt D. Beigel, Jigish D. Trivedi, Kevin G. Duesman
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Patent number: 8035160Abstract: Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.Type: GrantFiled: November 30, 2009Date of Patent: October 11, 2011Assignee: Micron Technology, Inc.Inventors: Kurt D. Beigel, Jigish D. Trivedi, Kevin G. Duesman
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Publication number: 20100276742Abstract: A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.Type: ApplicationFiled: July 12, 2010Publication date: November 4, 2010Inventors: Thomas W. Voshell, Lucien J. Bissey, Kevin G. Duesman
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Patent number: 7777264Abstract: A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.Type: GrantFiled: February 21, 2007Date of Patent: August 17, 2010Assignee: Micron Technology, Inc.Inventors: Thomas W. Voshell, Lucien J. Bissey, Kevin G. Duesman
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Patent number: 7730372Abstract: An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice, each having a test mode enable bond pad, such as an output enable pad. A fuse incorporated into the MCM's substrate connects each die's test mode enable bond pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable bond pads to one of the MCM's ground pins. By applying a supply voltage to the test mode enable bond pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a ground voltage applied to the test mode enable bond pads through the ground pins so the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging.Type: GrantFiled: September 18, 2008Date of Patent: June 1, 2010Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, James M. Wark, Eric S. Nelson, Kevin G. Duesman
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Publication number: 20100072532Abstract: Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.Type: ApplicationFiled: November 30, 2009Publication date: March 25, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Kurt D. Beigel, Jigish D. Trivedi, Kevin G. Duesman
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Patent number: 7645671Abstract: Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.Type: GrantFiled: November 13, 2006Date of Patent: January 12, 2010Assignee: Micron Technology, Inc.Inventors: Kurt D. Beigel, Jigish D. Trivedi, Kevin G. Duesman
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Patent number: 7519881Abstract: An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice, each having a test mode enable bond pad, such as an output enable pad. A fuse incorporated into the MCM's substrate connects each die's test mode enable bond pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable bond pads to one of the MCM's ground pins. By applying a supply voltage to the test mode enable bond pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a ground voltage applied to the test mode enable bond pads through the ground pins so the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging.Type: GrantFiled: March 27, 2006Date of Patent: April 14, 2009Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, James M. Wark, Eric S. Nelson, Kevin G. Duesman
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Publication number: 20090027076Abstract: An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice, each having a test mode enable bond pad, such as an output enable pad. A fuse incorporated into the MCM's substrate connects each die's test mode enable bond pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable bond pads to one of the MCM's ground pins. By applying a supply voltage to the test mode enable bond pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a ground voltage applied to the test mode enable bond pads through the ground pins so the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging.Type: ApplicationFiled: September 18, 2008Publication date: January 29, 2009Applicant: MICRON TECHNOLOGY, INC.Inventors: Warren M. Farnworth, James M. Wark, Eric S. Nelson, Kevin G. Duesman
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Publication number: 20080113478Abstract: Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.Type: ApplicationFiled: November 13, 2006Publication date: May 15, 2008Inventors: Kurt D. Beigel, Jigish D. Trivedi, Kevin G. Duesman
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Patent number: 7336522Abstract: A method and apparatus is provided for reducing the current in a memory device. Peripheral device control signals are translated to the wordline off voltage level, such as a negative wordline voltage. The translated signals prevent the peripheral devices from conducting current in the wordline off mode, even if a wordline-to-digitline short should occur. The control signals may include a column select signal for a column select device and an active pull-up signal for a sense amplifier, among others. Additionally, an equalization circuit having high and low resistance components is provided for the memory device. The equalization circuit limits current, even if a wordline-to-digitline short occurs.Type: GrantFiled: July 19, 2006Date of Patent: February 26, 2008Assignee: Micron Technology, Inc.Inventors: Scott J. Derner, Stephen R. Porter, Scot M. Graham, Ethan A. Williford, Kevin G. Duesman
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Patent number: 7276754Abstract: A memory structure having a vertically oriented access transistor with an annular gate region and a method for fabricating the structure. More specifically, a transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.Type: GrantFiled: August 4, 2005Date of Patent: October 2, 2007Assignee: Micron Technology, Inc.Inventors: Lucien J. Bissey, Kevin G. Duesman