Patents by Inventor Kuan-Yu Chen

Kuan-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140340830
    Abstract: An electronic device comprises a base, a display body, and a pivot mechanism. The pivot mechanism rotatably connects to the base and the display body to allow the display body to rotate relative to the base via the pivot mechanism. When one edge of the display body rotates to rest on the base, the pivot mechanism, the base, and the display body form a triangle to make the display body firmly supported by the pivot mechanism on the base.
    Type: Application
    Filed: May 16, 2014
    Publication date: November 20, 2014
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: KUO-HSIANG WU, KUAN-YU CHEN
  • Patent number: 8884299
    Abstract: A pixel structure of a display panel includes a gate line, a first data line, a second data line, a first active switching device, a second active switching device, a first pixel electrode and a second pixel electrode. The first pixel electrode is electrically connected to the first active switching device. The first pixel electrode includes a first main electrode disposed adjacent to one side of the first data line, and a second main electrode disposed adjacent to one side of the second data line. The second pixel electrode is electrically connected to the second active switching device. The second pixel electrode is disposed between the first main electrode and the second main electrode of the first pixel electrode.
    Type: Grant
    Filed: August 25, 2013
    Date of Patent: November 11, 2014
    Assignee: AU Optronics Corp.
    Inventors: Wei-Cheng Cheng, Kuan-Yu Chen, Tien-Lun Ting, Wen-Hao Hsu
  • Publication number: 20140313664
    Abstract: A folding electronic with protection against an opened cover pulling it over backwards has a base which includes at least one ejecting structure. A stability plate is fixed on the ejecting structure. When the cover is opened relative to the base, the stability plate extends from the base to provide additional support for the folding electronic device.
    Type: Application
    Filed: April 17, 2014
    Publication date: October 23, 2014
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: KUO-HSIANG WU, KUAN-YU CHEN
  • Publication number: 20140308790
    Abstract: In a method, a gate structure is formed over a substrate, and source/drain (S/D) features are formed in the substrate and interposed by the gate structure. At least one of the S/D features is formed by forming a first semiconductor material including physically discontinuous portions, forming a second semiconductor material over the first semiconductor material, and forming a third semiconductor material over the second semiconductor material. The second semiconductor material has a composition different from a composition of the first semiconductor material. The third semiconductor material has a composition different from the composition of the second semiconductor material.
    Type: Application
    Filed: June 26, 2014
    Publication date: October 16, 2014
    Inventors: Tsz-Mei KWOK, Hsueh-Chang SUNG, Kuan-Yu CHEN, Hsien-Hsin LIN
  • Patent number: 8846461
    Abstract: A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially pure silicon; and a second silicon-containing compound layer comprising the element on the silicon layer. The first and the second silicon-containing compound layers have substantially lower silicon concentrations than the silicon layer. The composite semiconductor structure may be formed as source/drain regions of metal-oxide-semiconductor (MOS) devices.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Hsin Lin, Weng Chang, Chien-Chang Su, Kuan-Yu Chen, Hsueh-Chang Sung, Ming-Hua Yu
  • Patent number: 8835982
    Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides a processing for forming improved lightly doped source/drain features and source/drain features in the semiconductor device. Semiconductor device with the improved lightly doped source/drain features and source/drain features may prevent or reduce defects and achieve high strain effect. In at least one embodiment, the lightly doped source/drain features and source/drain features comprises the same semiconductor material formed by epitaxial growth.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: September 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsz-Mei Kwok, Hsueh-Chang Sung, Kuan-Yu Chen, Hsien-Hsin Lin
  • Patent number: 8815713
    Abstract: A method includes forming a gate stack over a semiconductor substrate, forming an opening in the semiconductor substrate and adjacent to the gate stack, and performing a first epitaxy to grow a first semiconductor layer in the first opening. An etch-back is performed to reduce a thickness of the first semiconductor layer. A second epitaxy is performed to grow a second semiconductor layer over the first semiconductor layer. The first and the second semiconductor layers have different compositions.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsueh-Chang Sung, Tsz-Mei Kwok, Kuan-Yu Chen, Kun-Mu Li
  • Patent number: 8796788
    Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides a processing for forming improved source/drain features in the semiconductor device. Semiconductor devices with the improved source/drain features may prevent or reduce defects and achieve high strain effect resulting from epi layers. In an embodiment, the source/drain features comprises a second portion surrounding a first portion, and a third portion between the second portion and the semiconductor substrate, wherein the second portion has a composition different from the first and third portions.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: August 5, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsz-Mei Kwok, Hsueh-Chang Sung, Kuan-Yu Chen, Hsien-Hsin Lin
  • Publication number: 20140209978
    Abstract: A device includes a substrate, a gate structure over the substrate, and source/drain (S/D) features in the substrate and interposed by the gate structure. At least one of the S/D features includes a first semiconductor material, a second semiconductor material over the first semiconductor material, and a third semiconductor material over the second semiconductor material. The second semiconductor material has a composition different from the first semiconductor material and the third semiconductor material. The first semiconductor material includes physically discontinuous portions.
    Type: Application
    Filed: April 17, 2014
    Publication date: July 31, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsz-Mei KWOK, Hsueh-Chang SUNG, Kuan-Yu CHEN, Hsien-Hsin LIN
  • Publication number: 20140203302
    Abstract: A pixel structure of a display panel includes a gate line, a first data line, a second data line, a first active switching device, a second active switching device, a first pixel electrode and a second pixel electrode. The first pixel electrode is electrically connected to the first active switching device. The first pixel electrode includes a first main electrode disposed adjacent to one side of the first data line, and a second main electrode disposed adjacent to one side of the second data line. The second pixel electrode is electrically connected to the second active switching device. The second pixel electrode is disposed between the first main electrode and the second main electrode of the first pixel electrode.
    Type: Application
    Filed: August 25, 2013
    Publication date: July 24, 2014
    Applicant: AU Optronics Corp.
    Inventors: Wei-Cheng Cheng, Kuan-Yu Chen, Tien-Lun Ting, Wen-Hao Hsu
  • Publication number: 20140182914
    Abstract: A universal serial bus hybrid footprint design is described herein. The design includes an outer row of one or more surface mount technology (SMT) contacts and an inner row of one or more printed through holes (PTH). The hybrid footprint design enables a data through put of at least 10 Gbps.
    Type: Application
    Filed: December 27, 2012
    Publication date: July 3, 2014
    Inventors: Kuan-Yu Chen, Howard L. Heck
  • Publication number: 20140132582
    Abstract: A shift register circuit includes plural stages of shift registers. Each stage of shift register includes a pull-up circuit, a first driving circuit and a voltage-stabilizing circuit. The pull-up circuit is used for charging a first node. The first driving circuit is electrically connected with the first node. According to a voltage level of the first node, a corresponding control signal is outputted from an output terminal of the first driving circuit. The voltage-stabilizing circuit is electrically connected with the output terminal of the first driving circuit for stabilizing the control signal from the first driving circuit. Some circuits of some other shift registers are controlled according to the control signal.
    Type: Application
    Filed: January 21, 2014
    Publication date: May 15, 2014
    Applicant: AU OPTRONICS CORP.
    Inventors: Kuan-Yu CHEN, Wei-Cheng LIN
  • Patent number: 8724762
    Abstract: A clock regeneration method, for generating a clock signal for being utilized by a receiver/transceiver/receiver system/transceiver system, includes: performing data/pattern detection on at least one input signal to generate recovered data; detecting at least one synchronization pattern in the input signal according to a synchronization pattern rule, and generating a synchronization signal corresponding to the synchronization pattern; and performing frequency-locking on the synchronization signal to generate the clock signal. More particularly, the step of detecting the at least one synchronization pattern in the input signal according to the synchronization pattern rule further comprises: detecting the at least one synchronization pattern by performing synchronization pattern detection on the recovered data. An associated reference-less receiver and an associated crystal-less system are also provided.
    Type: Grant
    Filed: July 4, 2011
    Date of Patent: May 13, 2014
    Assignee: Faraday Technology Corp.
    Inventors: Yen-Yin Huang, Chauo-Min Chen, Kuan-Yu Chen, Yu-Sheng Yi, Ming-Shih Yu
  • Publication number: 20140127886
    Abstract: A method includes forming a gate stack over a semiconductor substrate, forming an opening in the semiconductor substrate and adjacent to the gate stack, and performing a first epitaxy to grow a first semiconductor layer in the first opening. An etch-back is performed to reduce a thickness of the first semiconductor layer. A second epitaxy is performed to grow a second semiconductor layer over the first semiconductor layer. The first and the second semiconductor layers have different compositions.
    Type: Application
    Filed: November 7, 2012
    Publication date: May 8, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsueh-Chang Sung, Tsz-Mei Kwok, Kuan-Yu Chen, Kun-Mu Li
  • Patent number: 8711077
    Abstract: An LCD device is configured to drive a plurality of shift register units using two clock signals having different driving abilities. Each shift register unit may thus generate a stronger signal for triggering a next-stage shift register unit, thereby improving cold-start. When the LCD device has been activated over a predetermined period of time, the driving ability of the clock signal having higher driving ability is gradually lowered, thereby reducing power consumption.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: April 29, 2014
    Assignee: AU Optronics Corp.
    Inventors: Kuan-Yu Chen, Yi-Suei Liao
  • Publication number: 20140092567
    Abstract: A clip assembly includes a seat having a surrounding wall with a receiving hole, and a locking mechanism proximate to the surrounding wall and including a pair of movable levers. Each movable lever has an engaging portion movably inserted into the receiving hole, and a driven portion. A drive unit has a button that is moved to a pressed position, where the driven portions are pushed to move away from each other and out of the receiving hole. A clip mechanism includes a connection body received in the receiving hole and having two connecting holes to respectively engage the engaging portions. The engaging portions are disengageable from the connecting holes by pressing the button.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 3, 2014
    Applicants: LITE-ON TECNOLOGY CORP., LITE-ON ELECTRONICS (GUANGZHOU) LIMITED
    Inventors: KUAN-YU CHEN, CHE-CHENG CHANG
  • Publication number: 20140085583
    Abstract: A display panel includes a pixel structure that has first, second, and third sub-pixels. In the first sub-pixel, a first pixel electrode having first branches and a second pixel electrode having second branches are alternately arranged. Gap dB is defined between adjacent first and second branches. In the second sub-pixel, a third pixel electrode having third branches and a fourth pixel electrode having fourth branches are alternately arranged. Gap dG is defined between adjacent third and fourth branches. In the third sub-pixel, a fifth pixel electrode having fifth branches and a sixth pixel electrode having sixth branches are alternately arranged. Gap dR is defined between adjacent fifth and sixth branches. The gaps dB, dG, and dR at least include minimum gaps dBmin, dGmin, and dRmin and gaps dBn, dGn, and dRn, respectively. Here, dGn is equal to dRn, and (1/dBn)?[(1/dRn)*1.1].
    Type: Application
    Filed: May 22, 2013
    Publication date: March 27, 2014
    Applicant: Au Optronics Corporation
    Inventors: Mei-Ju Lu, Cho-Yan Chen, Kuan-Yu Chen, Sau-Wen Tsao, Yen-Ying Kung, Tien-Lun Ting
  • Publication number: 20140085256
    Abstract: A capacitive touch sensor structure comprises a substrate, a first transmissive electrode, a first wire, a first receiving electrode and a second wire. The first transmissive electrode is disposed on the substrate and has at least one first electrode. The first wire is disposed on the substrate and connects to the first electrode of the first transmissive electrode. The first receiving electrode is disposed on the substrate and has at least one second electrode. The second wire is disposed on the substrate and extends along a first direction to connect to the first receiving electrode. The first electrode has a plurality of first slits and the second electrode has a plurality of second slits.
    Type: Application
    Filed: May 28, 2013
    Publication date: March 27, 2014
    Inventors: KUAN-YU CHEN, YU-FENG CHIEN, SEOK-LYUL LEE
  • Patent number: 8665250
    Abstract: A shift register circuit includes plural stages of shift registers. Each stage of shift register includes a pull-up circuit, a control signal generator and a voltage-stabilizing circuit. The pull-up circuit is used for charging a first node. The control signal generator is electrically connected with the first node. According to a voltage level of the first node, a corresponding control signal is outputted from an output terminal of the control signal generator. The voltage-stabilizing circuit is electrically connected with the output terminal of the control signal generator for stabilizing the control signal from the control signal generator. Some circuits of some other shift registers are controlled according to the control signal.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: March 4, 2014
    Assignee: Au Optronics Corp.
    Inventors: Kuan-Yu Chen, Wei-Cheng Lin
  • Patent number: RE45018
    Abstract: An electrical connector includes a housing member and a number of contacts attached to the housing member. The contacts include a number of first contacts and second contacts arranged side by side along a transverse direction, respectively. Each of the first and second contacts include a main portion, a contact portion and a bending portion extending from a lateral edge of the main portion. The bending portion has a narrow width in order to occupy small space of a rear wall of the housing member so that the rear wall of the housing member still has adequate area for mounting other components.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: July 15, 2014
    Assignee: Hon Hai Precision Ind. Co., Ltd.
    Inventors: Chong Yi, Kuan-Yu Chen