Abstract: A device matching verification method is provided. The device matching verification method includes reading, respectively, first color code information stored in a cradle device and second color code information stored in a memory device of an electronic device; transforming the first color code information to display a first color code on a first display region of a display device of the electronic device; transforming the second color code information to display a second color code on a second display region of the display device; and determining whether the cradle device matches the electronic device or not according to the first color code and the second color code.

Abstract: In one example an electronic device comprises a housing, a receptacle in the housing comprising an opening at a distal end to receive a plug, a data connector positioned in the receptacle to provide a communication connection, and an electrostatic conductor assembly positioned proximate the opening in the receptacle, wherein the electrostatic conductor assembly comprises a dedicated discharge path and a conductive pin mounted on a retention latch and moveable between a first position in which the conductive pin is in electrical contact with the data connector and a second position in which the conductive pin is not in electrical contact with the data connector. Other examples may be described.

Abstract: A low-temperature epitaxial method manufactures backside field stop layer of insulated gate bipolar transistor (IGBT) first provides a first conductive type substrate and fabricates front-side elements and front metal layer on a front side of the IGBT. A second conductive type impurity layer is formed on a back side of the first conductive type substrate by low-temperature epitaxial process and a collector metal layer is formed on bottom face of the first conductive type substrate.

Abstract: An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness.

Abstract: An electronic apparatus and an operating method of the electronic apparatus are provided. The electronic apparatus includes a display unit, a base, a touch pad and a processing unit. The base is coupled to the display unit. The touch pad is disposed on the base, includes touch areas and receives a touch action performed by the user on any touch area. The processing unit is coupled to the touch pad and sets a display frame of the display unit into display areas according to a position of each touch area, so that each touch area has the corresponding display area at a corresponding position on the display unit. After the touch pad received a first touch event, the processing unit obtains a first touch area where the first touch event is generated, and displays a first user interface in a first display area corresponding to the first touch area.

Abstract: An apparatus is described. The apparatus includes an add-on conductive attachment that includes a single piece of material. The add-on conductive attachment is to suppress radiation from a connector. The apparatus includes a plurality of ground pads, where at least one end-portion of the add-on conductive attachment is to couple with a ground pad of a printed circuit board (PCB) via at least one of the ground pads.

Abstract: A wearable display apparatus includes a reflective light modulator having a front, a light guide plate placed at the front of the light modulator, a plurality of monochromatic light sources of different colors, and an optical assembly. The light guide plate has a first and a second major surface opposite to each other, and a light incidence surface connected with the first and second major surfaces, the light guide plate directing light received at the light incidence surface through the first major surface toward the light modulator. The monochromatic light sources are operable to emit light of different colors in a sequential manner. The optical assembly is arranged adjacent to the light incidence surface of the light guide plate, and is configured to homogenize and distribute the light emitted by each of the monochromatic light sources across the light incidence surface.

Abstract: A FinFET device includes a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface. A fin of semiconductor material extends upwards from the substrate through an opening in the dielectric layer. A base portion of the fin, which is recessed below the upper dielectric layer surface, includes a base channel region that separates first and second base source/drain regions. An upper channel region extends upwards from the base channel region and terminates in an upper fin surface disposed above the upper dielectric layer surface. A gate electrode straddles the upper channel region and is separated from the upper channel region by a gate dielectric. First and second epitaxial source/drain regions meet the first and second base source/drain regions, respectively, at first and second interfaces, respectively. The first and second interfaces are recessed in the opening and arranged below the upper dielectric layer surface.

Abstract: An apparatus is described herein. The apparatus includes a receptacle to receive a plug to couple a peripheral device to a computing device. The apparatus includes a ground contact of a printed circuit board of the computing device. The apparatus includes a shield communicatively coupled to the ground contact, wherein the shield is to reduce radio frequency interference (RFI) from an interface between the plug and the receptacle.

Abstract: A low-temperature oxide method is used for manufacturing backside field stop layer of IGBT and first fabricates front elements and front metal layer on a first face of a first conductive type substrate. A multiple-recesses structure is formed on a back side of the first conductive type substrate. Each of the recess in the multiple-recesses structure has first conductive type implanted patterns on exterior sides thereof and the multiple-recesses structure has a first conductive type implanted layer on bottom thereof. A plurality of first conductive type polysilicon layers are deposited into the multiple-recesses structure and respectively corresponding to the first conductive type implanted patterns. A second conductive type impurity layer is formed on the bottom of the first conductive type substrate and laser annealing is conducted to form backside field stop layer for IGBT.

Abstract: Disclosed is an apparatus for pesticide detection in aqueous solution was provided, wherein an electrochemical biosensor, a container for mixing and an electrical signal analyzer were used, and the biosensor is disposable.

Abstract: The present invention relates to a method for fabricating a phosphor having a maximum absorption wavelength between 410 nm and 470 nm and having no rare earth elements therein and a method for generating a white light by using the phosphor having a maximum absorption wavelength between 410 nm and 470 nm and having no rare earth elements therein, and particularly relates to a method for fabricating manganese-doped zinc selenide nanoparticles, which can emit a yellow-orange light having a wavelength of 500 nm-700 nm, and a method for generating a white light by using the manganese-doped zinc selenide nanoparticles, which can emit a yellow-orange light having a wavelength of 500 nm-700 nm.

Abstract: In one example an electronic device comprises a housing. A receptacle in the housing comprising an opening at a distal end to receive a plug and an electrostatic conductor assembly positioned proximate the opening in the receptacle, wherein the electrostatic conductor assembly is coupled to a dedicated electrical discharge path. Other examples may be described.

Abstract: Methods and systems to support input output (IO) communications may include an IO connector having a housing with surfaces defining a paddle card region, and a set of compressible contacts extending vertically through the housing into the paddle card region. In addition, an IO interconnect can include a cable portion and at least one end portion coupled to the cable portion. The end portion may include a paddle card having a circuit board with a set of contacts disposed on a bottom surface of the circuit board. The end portion can also include an asymmetric metal shell having a configuration that encloses at least a portion of the paddle card and exposes the set of contacts.

Abstract: An apparatus is described. The apparatus includes an add-on conductive attachment that includes a single piece of material. The add-on conductive attachment is to suppress radiation from a connector. The apparatus includes a plurality of ground pads, where at least one end-portion of the add-on conductive attachment is to couple with a ground pad of a printed circuit board (PCB) via at least one of the ground pads.

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, forming a material layer over the substrate and the gate structure, implanting Ge, C, P, F, or B in the material layer, removing portions of the material layer overlying the substrate at either side of the gate structure, forming recesses in the substrate at either side of the gate structure, and depositing a semiconductor material in the recesses by an expitaxy process.

Abstract: An interconnect topology that includes vertical trench routing in a substrate is disclosed. In one embodiment, the interconnect comprises a substrate having a plurality of layers including a first ground plane layer; a pair of signal conductors that form a differential signal pair, each conductor of the pair of signal conductors having a first portion and a second portion, the second portion extending from the first portion into at least one of the plurality of layers, wherein width of the second portion is less than width of the first portion; and wherein the first ground plane layer is only a first partial layer and has a first void region that is closer to the pair of signal conductors than the first partial layer.

Abstract: Techniques for signal line connecting are described herein. An apparatus may include a first signal contact pad and a second signal contact pad adjacent to the first signal contact pad. The apparatus also includes a ground pad. The contact pads are disposed in an arrangement reducing inequality between unshielded lengths of a first signal line, a second signal line, and a drain line lines to be respectively connected to the first signal contact pad, the second signal contact pad, and the ground contact pad.

Abstract: Techniques for routing signal traces in a circuit board are described. An example of an electronic device in accordance with the described techniques includes a circuit board comprising a plurality of conductive layers. The conductive layers include a signal layer and a reference plane. The signal layer includes signal traces and the reference plane includes an additional signal trace.

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a plurality of fins, the fins being isolated from each other by an isolation structure, forming a gate structure over a portion of each fin; forming spacers on sidewalls of the gate structure, respectively, etching a remaining portion of each fin thereby forming a recess, epitaxially growing silicon to fill the recess including incorporating an impurity element selected from the group consisting of germanium (Ge), indium (In), and carbon (C), and doping the silicon epi with an n-type dopant.