Patents by Inventor Kuan-Yu Chen

Kuan-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9941611
    Abstract: Techniques and mechanisms for providing a reference potential with a flexible circuit device. In an embodiment, the flexible circuit device includes a first interconnect to exchange a signal and a second interconnect to exchange a reference potential that facilitates shielding of the signal. The first and second interconnects are variously coupled to a printed circuit board (PCB) via a first contact and a second contact of a hardware interface. During such coupling, a maximum height of the second interconnect from a side of the PCB at the hardware interface is greater than a maximum height of the first interconnect from the side of the PCB at the hardware interface. In another embodiment, a distance of the first contact from an end of the flexible circuit device is different than a distance of the second contact from the end of the flexible circuit device.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 10, 2018
    Assignee: INTEL CORPORATION
    Inventors: Kuan-yu Chen, Hao-han Hsu, Jingbo Li, Xiang Li
  • Patent number: 9911826
    Abstract: A device includes a substrate, a gate structure over the substrate, and source/drain (S/D) features in the substrate and interposed by the gate structure. At least one of the S/D features includes a first semiconductor material, a second semiconductor material over the first semiconductor material, and a third semiconductor material over the second semiconductor material. The second semiconductor material has a composition different from the first semiconductor material and the third semiconductor material. The first semiconductor material includes physically discontinuous portions.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: March 6, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsz-Mei Kwok, Hsueh-Chang Sung, Kuan-Yu Chen, Hsien-Hsin Lin
  • Publication number: 20180016499
    Abstract: The invention relates to a light modulation element comprising a cholesteric liquid crystalline medium sandwiched between two substrates (1), provided with a common electrode structure (2) and a driving electrode structure (3) individually, wherein the substrate with driving and/or common electrode structure is additionally provided with an alignment electrode structure (4) which is separated from the driving and or common electrode structure on the same substrate by a dielectric layer (5). The invention is further related to a method of production of said light modulation element and to the use of said light modulation element in various types of optical and electro-optical devices, such as electro-optical displays, liquid crystal displays (LCDs), non-linear optic (NLO) devices, and optical information storage devices.
    Type: Application
    Filed: December 30, 2015
    Publication date: January 18, 2018
    Applicant: MERCK PATENT GMBH
    Inventors: Ming-Chou WU, Kuan-Yu CHEN
  • Publication number: 20180004045
    Abstract: The invention relates to a light modulation element comprising a cholesteric liquid crystalline medium sandwiched between two substrates (1), provided with a common electrode structure (2) and a driving electrode structure (3) individually, wherein the substrate with driving and/or common electrode structure is additionally provided with an alignment electrode structure (4) which is separated from the driving and or common electrode structure on the same substrate by a dielectric layer (5), characterized in that it comprises at least one alignment layer (6) directly adjacent to the liquid crystalline medium. The invention is further related to a method of production of said light modulation element and to the use of said light modulation element in various types of optical and electro-optical devices, such as electro-optical displays, liquid crystal displays (LCDs), non-linear optic (NLO) devices, and optical information storage devices.
    Type: Application
    Filed: December 30, 2015
    Publication date: January 4, 2018
    Applicant: Merck Patent GmbH
    Inventors: Kuan-Yu CHEN, Ming-Chou WU, Bernd FIEBRANZ, Harald SEIBERT
  • Publication number: 20170357131
    Abstract: The invention relates to a light modulation element comprising a polymer stabilized cholesteric liquid crystalline medium sandwiched between two substrates (1), provided with a common electrode structure (2) and a driving electrode structure (3) individually, wherein the substrate with driving and/or common electrode structure is additionally provided with an alignment electrode structure (4) which is separated from the driving and or common electrode structure on the same substrate by an dielectric layer (5), characterized in that the light modulation element comprises at least one alignment layer (6) directly adjacent to the liquid crystalline medium. The invention is further relates to a method of production of said light modulation element and to the use of said light modulation element in various types of optical and electro-optical devices, such as electro-optical displays, liquid crystal displays (LCDs), non-linear optic (NLO) devices, and optical information storage devices.
    Type: Application
    Filed: January 5, 2016
    Publication date: December 14, 2017
    Applicant: MERCK PATENT GMBH
    Inventors: Kuan-Yu CHEN, Ming-Chou WU, Bernd FIEBRANZ, Harald SEIBERT
  • Patent number: 9842910
    Abstract: In a method, a gate structure is formed over a substrate, and source/drain (S/D) features are formed in the substrate and interposed by the gate structure. At least one of the S/D features is formed by forming a first semiconductor material including physically discontinuous portions, forming a second semiconductor material over the first semiconductor material, and forming a third semiconductor material over the second semiconductor material. The second semiconductor material has a composition different from a composition of the first semiconductor material. The third semiconductor material has a composition different from the composition of the second semiconductor material.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: December 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsz-Mei Kwok, Hsueh-Chang Sung, Kuan-Yu Chen, Hsien-Hsin Lin
  • Publication number: 20170310568
    Abstract: A maintenance method for network connection and a computer system are provided. The method is adapted to a computer system having a real-time clock. The real-time clock is configured to regularly wake up the computer system to check whether a network connection is working normally. In the method, a wake up operation to wake up the computer system is received from a user. It is determined whether a connection time of maintaining the network connection so far from a last time of entering a power saving mode is greater than a counting time for the real-time clock to wake up the computer system. It is tested whether the network connection is working normally when the connection time is greater than the counting time. The counting time of the real-time clock is updated to the connection time when the network connection is working normally.
    Type: Application
    Filed: July 10, 2017
    Publication date: October 26, 2017
    Applicant: Acer Incorporated
    Inventors: Kuan-Yu Chen, Shu-Chun Liao, Ching-Ho Tsai
  • Publication number: 20170261826
    Abstract: A pixel structure including a first data line, a first sub-pixel, and a second sub-pixel is disclosed. The first sub-pixel includes a first transistor and a first pixel electrode. A first end and a second end of the first transistor are connected to a first data line and the first pixel electrode, respectively. A distance between the first end and the first data line is less than a first width of the first pixel electrode. The second sub-pixel includes a second transistor and a second pixel electrode. A first end and a second end of the second transistor are connected to the first data line and the second pixel electrode, respectively. The first sub-pixel is disposed between the second sub-pixel and the first data line, and a distance between the first end of the second transistor and the first data line is less than the first width.
    Type: Application
    Filed: January 13, 2017
    Publication date: September 14, 2017
    Inventors: Yung-Yi CHEN, Chia-Yang CHENG, Kuan-Yu CHEN, Chun-Hsien YEH
  • Patent number: 9755334
    Abstract: A retention apparatus for a shielded cable is described. In one embodiment, the apparatus comprises a substrate having a ground; a connector coupled to the substrate; a cable shielded with a conductive material and having an end connectable to the connector to electrically connect with the connector; an electrically conductive material coupled to the ground of the substrate; and a grounding retention mechanism to cause the electrically conductive material to electrically connect the cable to the ground of the substrate by applying a force to the cable shield.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: September 5, 2017
    Assignee: INTEL CORPORATION
    Inventors: Xiang Li, Yun Ling, Chung-Hao J. Chen, Hao-Han Hsu, Shyamjith Mohan, Kuan-Yu Chen
  • Patent number: 9742653
    Abstract: A maintenance method for network connection and a computer system are provided. The method is adapted to a computer system having a real-time clock. The real-time clock is configured to regularly wake up the computer system to check whether a network connection is working normally. In the method, a wake up operation to wake up the computer system is received from a user. It is determined whether a connection time of maintaining the network connection so far from a last time of entering a power saving mode is greater than a counting time for the real-time clock to wake up the computer system. It is tested whether the network connection is working normally when the connection time is greater than the counting time. The counting time of the real-time clock is updated to the connection time when the network connection is working normally.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: August 22, 2017
    Assignee: Acer Incorporated
    Inventors: Kuan-Yu Chen, Shu-Chun Liao, Ching-Ho Tsai
  • Publication number: 20170186352
    Abstract: A shift register circuit includes a plurality of shift registers. Each shift register includes a driving module, a voltage pre-storing module, a pulling up module, a pulling down module and a pulling down control module. The voltage pre-storing module includes a reset unit, an electric power storage unit and an output unit. The driving module, the voltage pre-storing module and the reset unit are electrically connected to a first node. One end of the electric power storage unit is electrically connected to the first node, and the another end is configured to receive the touch start signal and the touch end signal. The output unit is electrically connected between the first node and the second node. The pulling up module and the pulling down module are electrically connected to the second node. The pulling down control module is electrically connected to the pulling down module.
    Type: Application
    Filed: December 9, 2016
    Publication date: June 29, 2017
    Inventors: Jia-Yi LIN, Kuan-Yu CHEN
  • Patent number: 9666691
    Abstract: A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chang Su, Tsz-Mei Kwok, Hsien-Hsin Lin, Hsueh-Chang Sung, Yi-Fang Pai, Kuan-Yu Chen
  • Publication number: 20170148889
    Abstract: A metal oxide semiconductor field effect transistor (MOSFET) power device with multi gates connection includes a first-conductive type substrate, a first-conductive type epitaxial layer arranged on the first-conductive type substrate, a plurality of device trenches defined on an upper face of the first-conductive type epitaxial layer. Each of the device trenches has, from bottom of the trench to top of the trench, a bottom gate, a split gate and a trench gate. A bottom insulating layer is formed between the bottom gate and the bottom of the trench, an intermediate insulating layer is formed between the bottom gate and the split gate, an upper insulating layer is formed between the split gate and the trench gate.
    Type: Application
    Filed: March 1, 2016
    Publication date: May 25, 2017
    Inventors: Kuan-Yu CHEN, Hsu-Heng LI, Mei-Ling CHEN
  • Publication number: 20170105999
    Abstract: The present invention relates to a method for treating a subject with a cancer resistant to a chemotherapeutic drug comprising administering to said subject a therapeutically effective amount of prochlorperazine or its analog or metabolite, or a pharmaceutically acceptable salt thereof, in combination of the chemotherapeutic drug. The present invention also relates to a method for preventing cancer metastasis with the combination of prochlorperazine in combination of a chemotherapeutic drug.
    Type: Application
    Filed: June 2, 2015
    Publication date: April 20, 2017
    Inventors: CHI-YING HUANG, PETER MU-HSIN CHANG, KUAN-YU CHEN, CHUN-HUNG WU, TAI-SHAN CHENG, CHENG-HAO YU
  • Publication number: 20170093059
    Abstract: Techniques and mechanisms for providing a reference potential with a flexible circuit device. In an embodiment, the flexible circuit device includes a first interconnect to exchange a signal and a second interconnect to exchange a reference potential that facilitates shielding of the signal. The first and second interconnects are variously coupled to a printed circuit board (PCB) via a first contact and a second contact of a hardware interface. During such coupling, a maximum height of the second interconnect from a side of the PCB at the hardware interface is greater than a maximum height of the first interconnect from the side of the PCB at the hardware interface. In another embodiment, a distance of the first contact from an end of the flexible circuit device is different than a distance of the second contact from the end of the flexible circuit device.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Inventors: Kuan-yu Chen, Hao-han Hsu, Jingbo Li, Xiang Li
  • Patent number: 9607564
    Abstract: A clock generator circuit of a liquid display panel includes a charge sharing switch unit, a first capacitor, a first switch, a second switch, a third switch and a fourth switch. The charge sharing switch unit is configured to receive control signals and accordingly output a first-polarity voltage to the first capacitor. The clock generator circuit is configured to turn on the first switch, the second switch, the third switch and the fourth switch according to a specific sequence thereby outputting a clock signal. An operation method for the aforementioned clock generator circuit is also provided.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: March 28, 2017
    Assignee: AU OPTRONICS CORP.
    Inventors: Chun-Kuei Wen, Yu-Ting Huang, Hung-Min Shih, Kuan-Yu Chen
  • Patent number: 9596749
    Abstract: Techniques for routing signal traces in a circuit board are described. An example of an electronic device in accordance with the described techniques includes a circuit board comprising a plurality of conductive layers. The conductive layers include a signal layer and a reference plane. The signal layer includes signal traces and the reference plane includes an additional signal trace.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: March 14, 2017
    Assignee: Intel Corporation
    Inventors: Kuan-Yu Chen, Yun Ling, Mohd Muhaiyiddin Bin Abdullah, Jackson Chung Peng Kong, Chung-Hao Chen, Hao-Han Hsu, Xiang Li
  • Patent number: 9582069
    Abstract: An electronic apparatus having an input unit and a network card and a wake-up method thereof are provided. In the method, an input event triggered by the input unit is received. Next, whether the electronic apparatus is in a partial wake-up mode entered after being woken up by the network card is determined. Then, the electronic apparatus is woken up to a normal operation mode if the electronic apparatus is in the partial wake-up mode.
    Type: Grant
    Filed: December 25, 2014
    Date of Patent: February 28, 2017
    Assignee: Acer Incorporated
    Inventors: Kuan-Yu Chen, Shu-Chun Liao, Ching-Ho Tsai
  • Patent number: 9570561
    Abstract: Some embodiments relate to an integrated circuit (IC) including one or more finFET devices. A finFET includes a fin of semiconductor material extending upwards from a semiconductor substrate. First and second source/drain regions, which have a first doping type, are spaced apart laterally from one another in the fin. A channel region is disposed in the fin and physically separates the first and second source/drain regions from one another. The channel region has a second doping type opposite the first doping type. A conductive gate electrode straddles the fin about the channel region and is separated from the channel region by a gate dielectric. A shallow doped region, which has the first doping type, is disposed near a surface of the fin around upper and sidewall fin regions. The shallow doped region extends continuously under the gate electrode between outer edges of the gate electrode.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: February 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ru-Shang Hsiao, Yi-Ju Chen, Sheng-Fu Yu, I-Shan Huang, Kuan Yu Chen, Li-Yi Chen
  • Patent number: 9543399
    Abstract: A semiconductor device having an open profile gate electrode, and a method of manufacture, are provided. A funnel-shaped opening is formed in a dielectric layer and a gate electrode is formed in the funnel-shaped opening, thereby providing a gate electrode having an open profile. In some embodiments, first and second gate spacers are formed alongside a dummy gate electrode. The dummy gate electrode is removed and upper portions of the first and second gate spacers are removed. The first and second gate spacers may be formed of different materials having different etch rates.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: January 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Shang Hsiao, Ling-Sung Wang, Chih-Mu Huang, Yao-Tsung Chen, Ming-Tsang Tsai, Kuan-Yu Chen