Patents by Inventor Kun Yuan

Kun Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160074275
    Abstract: The constant hot temperature flat massage ball comprises one top shell-shaped receptacle, one bottom shell-shaped receptacle and a central heating unit which is either a hot water bag, which has circulating water tube, a water pump and a precision temperature control hot water reservoir equipped with a thermostat, or an electric heating pad, which has an electric cord and a thermostat. The top shell-shaped receptacle has a central recess to store the heating unit and a circular female threaded wall at the upper portion of central recess. The bottom shell-shaped receptacle also has a central recess to store the heating unit, a circular male threaded embankment above the central recess to screw into the above-mentioned circular female threaded wall and a groove which is built transversely across its wall and the above-mentioned male threaded embankment to admit the above mentioned circulating water tube and electric cord.
    Type: Application
    Filed: September 11, 2014
    Publication date: March 17, 2016
    Inventor: Kun Yuan Tong
  • Publication number: 20160071944
    Abstract: A semiconductor device having metal gate includes a substrate, a first metal gate positioned on the substrate, and a second metal gate positioned on the substrate. The first metal gate includes a first work function metal layer, and the first work function metal layer includes a taper top. The second metal gate includes a second work function metal layer. The first work function metal layer and the second work function metal layer are complementary to each other.
    Type: Application
    Filed: October 9, 2014
    Publication date: March 10, 2016
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang
  • Publication number: 20160064528
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a metal gate thereon and a hard mask atop the metal gate; and performing a high-density plasma (HDP) process to form a cap layer on the hard mask and the substrate.
    Type: Application
    Filed: October 8, 2014
    Publication date: March 3, 2016
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang
  • Publication number: 20160053577
    Abstract: In one aspect, an apparatus for use in a wellbore is disclosed, including: an inlet; an outlet; and a variable flow restriction configured to provide a predetermined constant pressure drop between the inlet and the outlet in response to a range of inlet flow rates. In another aspect, a method for providing a fluid flow within a wellbore is disclosed, including: providing the fluid flow to an inlet; restricting the fluid flow to provide a predetermined constant pressure drop between the inlet and an outlet in response to a range of fluid flow rates; and providing the fluid flow to the wellbore from the outlet.
    Type: Application
    Filed: August 22, 2014
    Publication date: February 25, 2016
    Applicant: Baker Hughes Incorporated
    Inventors: Zhi Yong He, Madhawa Ratnayake, Kun Yuan, Carlos P. Izaguirre, David Teale, Darrin L. Willauer
  • Patent number: 9263294
    Abstract: A method of forming a semiconductor device is provided. A material layer, a first flowing material layer and a first mask layer are sequentially formed on a substrate. A first etching process is performed by using the first mask layer as a mask, so as to form a first opening in the material layer. The first mask layer and the first flowing material layer are removed. A filler layer is formed in the first opening. A second flowing material layer is formed on the material layer and the filler layer. A second mask layer is formed on the second flowing material layer. A second etching process is performed by using the second mask layer as a mask, so as to form a second opening in the material layer.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: February 16, 2016
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chieh-Te Chen, Cheng-Hsing Chuang
  • Patent number: 9263540
    Abstract: The metal gate structure includes at least a substrate, a dielectric layer, first and second trenches, first metal layer and second metal layers, and two cap layers. In particular, the dielectric layer is disposed on the substrate, and the first and second trenches are disposed in the dielectric layer. The width of the first trench is less than the width of the second trench. The first and second metal layers are respectively disposed in the first trench and the second trench, and the height of the first metal layer is less than or equal to the height of the second metal layer. The cap layers are respectively disposed in a top surface of the first metal layer and a top surface of the second metal layer.
    Type: Grant
    Filed: September 13, 2015
    Date of Patent: February 16, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Chih-Sen Huang, Shih-Fang Tzou, Chien-Ting Lin, Yi-Wei Chen, Shi-Xiong Lin, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Hsiao-Pang Chou, Chia-Lin Lu
  • Publication number: 20160043030
    Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a first dielectric layer, and a first metal plug structure, wherein a circuit element is disposed on the substrate. The first dielectric layer is disposed on the circuit element and on the substrate. The first metal plug structure, including a first barrier metal layer and a first metal interconnector, is embedded in the first dielectric layer. The first metal interconnector is in direct contact with the circuit element. The first barrier metal layer is disposed on the first metal interconnector; wherein the first barrier metal layer and the first metal interconnect have different metal materials.
    Type: Application
    Filed: September 4, 2014
    Publication date: February 11, 2016
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: CHIA-LIN LU, CHUN-LUNG CHEN, KUN-YUAN LIAO, FENG-YI CHANG
  • Publication number: 20160039104
    Abstract: When two conventional safety razor double-edged blades are superposed on top of each other, there is no space in between them to pass the shaving residues. The presently invented safety razor double-edged blade is equipped with several spaced protuberances on its surface. When two of these present invented blades are overlapped, there is a space between them to pass the shaving residues to be rinsed away by running water. Therefore two, three or more of them can be superposed on a single razor blade holder to allow the user to experience all the benefits of a multi-blade razor cartridge in a safety razor blade system.
    Type: Application
    Filed: August 11, 2014
    Publication date: February 11, 2016
    Inventor: Kun Yuan Tong
  • Publication number: 20160027892
    Abstract: The metal gate structure includes at least a substrate, a dielectric layer, first and second trenches, first metal layer and second metal layers, and two cap layers. In particular, the dielectric layer is disposed on the substrate, and the first and second trenches are disposed in the dielectric layer. The width of the first trench is less than the width of the second trench. The first and second metal layers are respectively disposed in the first trench and the second trench, and the height of the first metal layer is less than or equal to the height of the second metal layer. The cap layers are respectively disposed in a top surface of the first metal layer and a top surface of the second metal layer.
    Type: Application
    Filed: September 13, 2015
    Publication date: January 28, 2016
    Inventors: Ching-Ling Lin, Chih-Sen Huang, Shih-Fang Tzou, Chien-Ting Lin, Yi-Wei Chen, Shi-Xiong Lin, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Hsiao-Pang Chou, Chia-Lin Lu
  • Publication number: 20160027885
    Abstract: A method for fabricating a field-effect transistor is provided. The method includes: forming a gate dielectric layer and a barrier layer on a substrate in sequence; forming a first silicon layer on and in contact with the barrier layer; performing a thermal treatment to form a silicide layer between the barrier layer and the first silicon layer; and forming a second silicon layer on and in contact with the first silicon layer.
    Type: Application
    Filed: October 2, 2015
    Publication date: January 28, 2016
    Inventors: Kun-Yuan LO, Chih-Wei YANG, Cheng-Guo CHEN, Rai-Min HUANG, Jian-Cun KE
  • Patent number: 9243953
    Abstract: The present disclosure provides a spectrophotometric colorimeter based on LED light source, wherein the spectrophotometric colorimeter includes an integrating sphere, a coupling light path, and a spectrometer. An inner wall of the integrating sphere is arranged with a composite light source consisting of eight LEDs; a sphere wall of the integrating sphere defines an incident aperture; light emitted from each LED enters an interior of the integrating sphere through the incident aperture and is irradiated onto the inner wall. The coupling light path is configured to couple light at a measurement caliber such that the light can enter an incident split and to eliminate stray light from the inner wall.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: January 26, 2016
    Assignees: HANGZHOU CHNSPEC TECHNOLOGY CO. LTD, CHINA JILIANG UNIVERSITY
    Inventors: Kun Yuan, Yiping Wu, Cong Wang, Shangzhong Jin
  • Publication number: 20160020144
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a device thereon; forming a dielectric layer on the device and the substrate; forming a first mask layer on the dielectric layer; removing part of the first mask layer and part of the dielectric layer for forming a patterned first mask layer on the dielectric layer; covering a hard mask on the patterned first mask layer and the dielectric layer; partially removing the hard mask for forming a spacer adjacent to the patterned first mask layer and the dielectric layer; forming a contact hole adjacent to the spacer; filling the contact hole with a metal layer; and planarizing the metal layer for forming a contact plug, wherein the contact plug contacts the dielectric layer and the spacer simultaneously.
    Type: Application
    Filed: July 15, 2014
    Publication date: January 21, 2016
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chieh-Te Chen
  • Publication number: 20160005658
    Abstract: A metal gate structure includes a substrate including a dense region and an iso region. A first metal gate structure is disposed within the dense region, and a second metal gate structure is disposed within the iso region. The first metal gate structure includes a first trench disposed within the dense region, and a first metal layer disposed within the first trench. The second metal gate structure includes a second trench disposed within the iso region, and a second metal layer disposed within the second trench. The height of the second metal layer is greater than the height of the first metal layer.
    Type: Application
    Filed: August 19, 2014
    Publication date: January 7, 2016
    Inventors: Shi-Xiong Lin, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Yu-Cheng Tung
  • Patent number: 9230864
    Abstract: A method of forming a semiconductor device having a metal gate includes the following steps. First of all, a first gate trench is formed in a dielectric layer. Next, a first work function layer is formed, covering the first gate trench. Then, a protection layer is formed in the first gate trench, also on the first work function layer. Then, a patterned sacrificial mask layer is formed in the first gate trench to expose a portion of the protection layer. After that, the exposed protection layer is removed, to form a U-shaped protection layer in the first gate trench. As following, a portion of the first work function layer under the exposed protection layer is removed, to form a U-shaped first work function layer in the first gate trench. Finally, the patterned sacrificial mask layer and the U-shaped protection layer are completely removed.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: January 5, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Shi-Xiong Lin
  • Publication number: 20150375031
    Abstract: An Exercise tube with adjustable resistance can provide different compression resistance strength for exercise. A user can select the correct spring loaded small tubes of different resistance strength to add up to desired total resistance strength and insert them into bigger outer tube and big inner tube. The user can adjust the resistance strength needed for a particular exercise. In addition, different user can share the same exercise tube by adjusting the resistance strength to suit their individual needs.
    Type: Application
    Filed: June 27, 2014
    Publication date: December 31, 2015
    Inventor: Kun Yuan Tong
  • Publication number: 20150375032
    Abstract: The adjustable variant resistance exercise apparatus has installed several different resistant elastic springs and can provide variety of resistance for exercise. Man, woman, boy and girl can share the same one of adjustable variant resistance exercise apparatus for exercise. User can upgrade or downgrade exercise resistant power by adding more or remove some elastic rubber bands for exercise.
    Type: Application
    Filed: June 27, 2014
    Publication date: December 31, 2015
    Inventor: Kun Yuan Tong
  • Patent number: 9214392
    Abstract: A method of forming a contact hole includes providing a substrate. A nitrogen-containing dielectric layer, a first material layer, a second material layer, an oxygen-containing dielectric layer and a patterned photoresist layer cover the substrate from bottom to top. Then, the oxygen-containing dielectric layer is etched by taking the second material layer as a first etching stop layer to form a patterned oxygen-containing dielectric layer. Latter, the second material layer is etched by taking the first material layer as a second etching stop layer to form a patterned second material layer. Subsequently, the first material layer is etched by taking the nitrogen-containing dielectric layer as a third etching stop layer to form a patterned first material layer. Finally, the nitrogen-containing dielectric layer is etched until the substrate is exposed.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: December 15, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang
  • Patent number: 9209273
    Abstract: A method for fabricating a metal gate structure includes providing a substrate on which a dielectric layer, a first trench disposed in the dielectric layer, a first metal layer filling up the first trench, a second trench disposed in the dielectric layer, a second metal layer filling up the second trench are disposed, and the width of the first trench is less than the width of the second trench; forming a mask layer to completely cover the second trench; performing a first etching process to remove portions of the first metal layer when the second trench is covered by the mask layer; and performing a second etching process to concurrently remove portions of the first metal layer and portions of the second metal layer after the first etching process.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: December 8, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Chih-Sen Huang, Shih-Fang Tzou, Chien-Ting Lin, Yi-Wei Chen, Shi-Xiong Lin, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Hsiao-Pang Chou, Chia-Lin Lu
  • Publication number: 20150325453
    Abstract: A method of forming a semiconductor device is provided. A material layer, a first flowing material layer and a first mask layer are sequentially formed on a substrate. A first etching process is performed by using the first mask layer as a mask, so as to form a first opening in the material layer. The first mask layer and the first flowing material layer are removed. A filler layer is formed in the first opening. A second flowing material layer is formed on the material layer and the filler layer. A second mask layer is formed on the second flowing material layer. A second etching process is performed by using the second mask layer as a mask, so as to form a second opening in the material layer.
    Type: Application
    Filed: May 8, 2014
    Publication date: November 12, 2015
    Applicant: United Microelectronics Corp.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chieh-Te Chen, Cheng-Hsing Chuang
  • Patent number: 9184254
    Abstract: A field-effect transistor comprises a substrate, a gate dielectric layer, a barrier layer, a metal gate electrode and a source/drain structure. The gate dielectric layer is disposed on the substrate. The barrier layer having a titanium-rich surface is disposed on the gate dielectric layer. The metal gate electrode is disposed on the titanium-diffused surface. The source/drain structure is formed in the substrate and adjacent to the metal gate electrode.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: November 10, 2015
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Kun-Yuan Lo, Chih-Wei Yang, Cheng-Guo Chen, Rai-Min Huang, Jian-Cun Ke