Abstract: Various embodiments of the present invention relate to a secondary battery. The technical problem to be solved is to provide the secondary battery which can improve the insulation strength of first and second multi-tabs, by forming the first and second multi-tabs of first and second electrode assemblies symmetrically with respect to each other, and also can improve the insulation strength of the first and second multi-tabs by forming an insulating layer on the first and second multi-tabs of the first and second electrode assemblies.

Abstract: A semiconductor memory device includes a peripheral circuit structure including a peripheral circuit insulating layer, a middle connection structure on the peripheral circuit insulating layer, the middle connection structure including a middle connection insulating layer, and a bottom surface of the middle connection insulating layer is in contact with a top surface of the peripheral circuit insulating layer, stack structures on sides of the middle connection structure, and channel structures extending vertically through each of the stack structures, wherein at least one side surface of the middle connection insulating layer is an inclined surface, a lateral sectional area of the middle connection insulating layer decreasing in an upward direction oriented away from the peripheral circuit insulating layer.

Abstract: An integrated circuit (IC) device includes: a channel region that extends on the substrate to penetrate a plurality of word lines; a bit line contact pad that contacts an upper surface of the channel region; a bit line that contacts the bit line contact pad and extends on the bit line contact pad in a direction parallel to the main surface of the substrate; a common source line that partially fills a word line cut region and has a height lower than that of the channel region; and a common source via contact that contacts an upper surface of the common source line in the word line cut region.

Abstract: A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.

Abstract: Various embodiments of the present invention relate to a secondary battery having a structure for suppressing multi-tab short circuits, and the technical problem to be solved is providing a secondary battery capable of increasing the insulation level of multi-tabs by forming insulating layers on the multi-tabs of an electrode assembly. To this end, the present invention provides a secondary battery comprising: a case; an electrode assembly accommodated inside the case and having multi-tabs; and a cap plate closing the case and having electrode terminals electrically connected to the multi-tabs of the electrode assembly, wherein the surfaces of the multi-tabs are coated with insulating layers.

Abstract: A three-dimensional semiconductor memory device includes: a base substrate; a gate stack structure disposed on the base substrate, and including gate electrodes stacked in a direction substantially perpendicular to a top surface of the base substrate; a penetration region penetrating through the gate stack structure and surrounded by the gate stack structure; and vertical channel structures passing through the gate stack structure. The lowermost gate electrodes among the gate electrodes are spaced apart from each other, and a portion of at least one of the lowermost gate electrodes has a shape bent toward the penetration region.

Abstract: Three-dimensional semiconductor memory devices are provided. The devices may include a semiconductor layer and electrode structures on the semiconductor layer. The electrode structures may include a first electrode structure including a first electrode portion and a first pad portion and a second electrode structure including a second electrode portion and a second pad portion. Each of the first and second electrode portions has a first width, each of the first and second pad portions has a second width, and the second width may be less than the first width. The first and second electrode portions may be spaced apart from each other by a first distance, and the first and second pad portions may be spaced apart from each other by a second distance that may be greater than the first distance.

Abstract: Disclosed herein are methods of generating induced pluripotent stem cells. The method involves providing a somatic or non-embryonic cell population, contacting the somatic or non-embryonic cell population with a quantity of at least one reprogramming factor, an agent that downmodulates SIRT2, and/or an agent that upmodulates SIRT1, and culturing the somatic or non-embryonic cells for a period of time sufficient to generate at least one induced pluripotent stem cell. Methods for differentiating a cell by upmodulating SIRT2 and/or downmodulating SIRT1 are also provided herein. Also disclosed are cell lines and pharmaceutical compositions generated by use of the methods.

Abstract: Disclosed are an apparatus for and a method of performing an inspection and metrology process. The apparatus may include a stage configured to load a substrate thereon, a sensor on the stage, an object lens between the sensor and the stage, a light source generating an illumination light to be transmitted to the substrate through the object lens, a first band filtering part between the light source and the object lens to control a wavelength of the illumination light within a first bandwidth, and a second band filtering part between the light source and the object lens to control a wavelength of the illumination light within a second bandwidth, which is smaller than the first bandwidth.

Abstract: A three-dimensional semiconductor memory device includes first and second gate stacked structures, disposed on a base substrate, and stacked in a direction perpendicular to a surface of the base plate, the first and second gate stacked structures including gate electrodes spaced apart from each other and stacked; a through region passing through the first and second gate stacked structures and surrounded by the first and second gate stacked structures; and vertical channel structures passing through the first and second gate stacked structures, wherein the first gate stacked structure has first contact pads adjacent to the through region and arranged in a stepped shape, the second gate stacked structure having second contact pads adjacent to the through region and arranged in a stepped shape, at least a portion of the second contact pads overlap the first contact pads on one side of the through region.

Abstract: Embodiments of the invention relate to a secondary battery having symmetric multi-tabs, and the technical problem to be solved is providing a secondary battery capable of increasing the insulation level of first and second multi-tabs by forming the first and second multi-tabs of first and second electrode assemblies to be symmetric to each other. To this end, the present invention provides a secondary battery comprising: a case; a first electrode assembly accommodated inside the case and having first multi-tabs; a second electrode assembly accommodated in parallel with the first electrode assembly inside the case and having second multi-tabs; and a cap plate closing the case and having electrode terminals electrically connected to the first and second multi-tabs of the first and second electrode assemblies, wherein the first and second multi-tabs are formed so as to be symmetrical with respect to the boundary area between the first and second electrode assemblies.

Abstract: An inspection apparatus includes a light source device providing incident light to a substrate, an objective lens receiving reflection light reflected from the substrate, a light splitting device disposed over the objective lens, first and second optical sensors disposed at both sides of the light splitting device, respectively, and first and second spatial filters disposed between the first optical sensor and the substrate and between the second optical sensor and the substrate, respectively. The first and second spatial filters transmit the reflection light in different forms from each other.

Abstract: Provided are an emergency stop apparatus including a switch unit installed in a work space, electrically connected to a facility, and operable by pulling and a wire which is disposed in the work space so that tension is applied and of which at least one side is detachably mounted on the switch unit and an emergency stop method for quickly stopping the facility at a desired position within the work space in a manner of pulling or pushing the wire.

Abstract: A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, and having a gate insulating layer and a channel layer, a common source extension region including a first semiconductor layer having an n-type conductivity between the substrate and the channel structures, a plurality of gate electrodes on the common source extension region and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension region and including a second semiconductor layer having an n-type conductivity, wherein the gate insulating layer of each of the channel structures extends to cover an upper surface and at least a portion of a bottom surface of the common source extension region.

Abstract: A three-dimensional semiconductor device is provided including main separation structures disposed on a substrate, and extending in a first direction, parallel to a surface of the substrate; gate electrodes disposed between the main separation structures; a first secondary separation structure penetrating through the gate electrodes, between the main separation structures, and including a first linear portion and a second linear portion, having end portions opposing each other; and second secondary separation structures disposed between the first secondary separation structure and the main separation structures, and penetrating through the gate electrodes. The second secondary separation structures have end portions opposing each other between the second linear portion and the main separation structures.

Abstract: An imaging apparatus includes an illumination light source to output an illumination light, an illumination optical system to transmit the illumination light toward a sample, an imaging optical system to transmit light reflected from the sample, a stage to move the sample in a predetermined transfer direction, and a photographing unit to receive the reflected light. The imaging apparatus may include one or more diffraction grids located at conjugate focal planes of the sample. The operation of the photographing unit may be synchronized with a movement of the sample by the stage to obtain an image in accordance with a time delay integration method.

Abstract: The present invention discloses an arched steel fiber for reinforcement of a cement-based material, of which a main body is arched in a length direction and opposite ends of the main body are curved such that the steel fiber has a higher pullout resistance strength compared to a conventional steel fiber, thereby improving mechanical performance such as a tensile strength, a flexural strength, an energy absorption capability, and the like of a cement compound. In addition, compared to a conventional art, a mixing amount of steel fiber to performance can be reduced so that an added economic value in terms of consumable cost can be created.

Abstract: A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, and having a gate insulating layer and a channel layer, a common source extension region including a first semiconductor layer having an n-type conductivity between the substrate and the channel structures, a plurality of gate electrodes on the common source extension region and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension region and including a second semiconductor layer having an n-type conductivity, wherein the gate insulating layer of each of the channel structures extends to cover an upper surface and at least a portion of a bottom surface of the common source extension region.

Abstract: The present invention relates to a saccharide syrup composition comprising an organic acid or its salt and an oligosaccharide, and more specifically, the saccharide syrup composition comprises allulose.

Abstract: A vertical non-volatile memory device includes a substrate including a cell region; a lower insulating layer on the substrate; a lower wiring pattern in the cell region having a predetermined pattern and connected to the substrate through the lower insulating layer; and a plurality of vertical channel layers extending in a vertical direction with respect to a top surface of the substrate in the cell region, spaced apart from one another in a horizontal direction with respect to the top surface of the substrate, and electrically connected to the lower wiring pattern. The memory device also includes a plurality of gate electrodes stacked alternately with interlayer insulating layers in the cell region in the vertical direction along a side wall of a vertical channel layer and formed to extend in a first direction along the horizontal direction.