Abstract: Provided is a method and apparatus for speech synthesis of a text message. The method includes receiving input of voice parameters for a text message, storing each of the text message and the input voice parameters in a data packet, and transmitting the data packet to a receiving terminal.

Abstract: In a bonding configuration for a semiconductor device package, the bonding angles of the bonding wires are maintained within acceptable limits, without causing an increase in the chip die size, and without necessitating the use of the corner rule. In this manner, the occurrence of shorting between adjacent bonding wires can be mitigated or eliminated, and device net die count during fabrication can be increased.

Abstract: Embodiments of the invention provide a method for fabricating a system in package. In one embodiment, the method comprises preparing a printed circuit board (PCB) strip comprising a plurality of individual PCBs, stacking a plurality of first semiconductor chips and forming an encapsulant on a first surface of a first individual PCB of the plurality of individual PCBs to form a first semiconductor chip stack structure comprising a first semiconductor chip stack, and performing a first test adapted to test one of the first semiconductor chips in the first semiconductor chip stack. The method further comprises flip chip bonding a second semiconductor chip to a second surface of the first individual PCB if the first semiconductor chip stack structure meets a test standard based on a result of the first test, and dividing the first semiconductor chip stack structure to form a system in package.

Abstract: Disclosed is a semiconductor device packaging technique that is capable of resolving a problem of instability of bonding wires when stacking a plurality of semiconductor chips. The technique is also capable of realizing a slim, light and small package. The semiconductor device package includes a substrate having a substrate pad on a surface thereof, one or more memory chips stacked on the substrate with each memory chip having a pad connected to a common pin receiving a common signal applied to all the memory chips, an interposer chip stacked on the substrate and having an interconnection wire connected to the memory chip pad, the common pin of each of the memory chips being electrically connected to the interconnection wire via the memory chip pad, and a logic chip stacked on the substrate and having a bypass circuit which electrically connects or disconnects the interconnection wire to or from the substrate pad.

Abstract: Embodiments of the invention provide a method for fabricating a system in package. In one embodiment, the method comprises preparing a printed circuit board (PCB) strip comprising a plurality of individual PCBs, stacking a plurality of first semiconductor chips and forming an encapsulant on a first surface of a first individual PCB of the plurality of individual PCBs to form a first semiconductor chip stack structure comprising a first semiconductor chip stack, and performing a first test adapted to test one of the first semiconductor chips in the first semiconductor chip stack. The method further comprises flip chip bonding a second semiconductor chip to a second surface of the first individual PCB if the first semiconductor chip stack structure meets a test standard based on a result of the first test, and dividing the first semiconductor chip stack structure to form a system in package.

Abstract: A chip stack package may include a substrate, semiconductor chips, a molding member and a controller. The substrate may have a wiring pattern. The semiconductor chips may be stacked on a first surface of the substrate. Further, the semiconductor chips may be electrically connected to the wiring pattern. The molding member may be formed on the first substrate covering the semiconductor chips. The controller may be arranged on a second surface of the substrate. The controller may be electrically connected to the wiring pattern. The controller may have a selection function for selecting operable semiconductor chip(s) among the semiconductor chips.

Abstract: A stacked semiconductor package can be formed according to principles of the present invention by stacking a plurality of semiconductor packages. A method of manufacturing the stacked semiconductor packages provides a simple manufacturing process. The stacked semiconductor package embodying these principles preferably includes a base substrate, one or more lower semiconductor packages, one or more upper semiconductor packages, and an external sealing agent. Each lower semiconductor package can include a first inner substrate, one or more first semiconductor chips electrically connected to and mounted on the first inner substrate, a first inner sealing agent sealing the first semiconductor chips, and a first contact portion. Each lower semiconductor package is preferably mounted on a portion of an upper surface of the base substrate and is electrically connected to the base substrate via the first contact portion.

Abstract: A method and apparatus for encoding/decoding an image that divide an image sequence into sub-groups and determine encoding modes applied to bi-directional pictures included in each sub-group using correlations between the bi-directional pictures and reference pictures are provided. The image encoding method includes dividing a group of pictures (GOP) to be encoded according to consecutive B pictures into sub-groups; calculating the correlations between each B picture included in the sub-group and reference picture according to each encoding mode; and applying one of the encoding modes wherein the reference picture having the highest correlation with the B picture are used in each sub-group to encode the image, thereby improving encoding efficiency.

Abstract: A method of manufacturing a multi-stack package that ensures easy application of a solder paste or a flux. The method includes forming a first package comprising a first substrate on which bumps are arranged and a second package comprising a second substrate on which electrode pads corresponding to the bumps are arranged, applying a solder paste on the bumps of the first package, and electrically connecting the bumps of the first package and the electrode pads of the second package.

Abstract: A stacked semiconductor package may include a wiring substrate. A first semiconductor chip may be disposed on the wiring substrate and wire-bonded to the wiring substrate. An interposer chip may be disposed on the wiring substrate and sire bonded to the wiring substrate. The interposer chip may include a circuit element and a bonding pad being electrically connected. A second semiconductor chip may be disposed on the interposer chip and wire-bonded to the interposer chip. The second semiconductor chip may be electrically connected to the wiring substrate through the interposer chip.

Abstract: A vertical stack type multi-chip package is provided having improved reliability by increasing the grounding performance and preventing the decrease in reliability of the multi-chip package from moisture penetration into a lower semiconductor chip. The vertical stack type multi-chip package comprises an organic substrate having a printed circuit pattern on which a semiconductor chip is mounted. A first semiconductor chip is mounted on a die bonding region of the organic substrate and is electrically connected to the organic substrate through a first wire. A metal stiffener is formed on the first semiconductor chip and connected to the organic substrate by a first ground unit around the first semiconductor chip. An encapsulant is used to seal the first semiconductor chip below the metal stiffener. A second semiconductor chip, which is larger in size than that the first semiconductor chip, is mounted on the metal stiffener and connected by a second ground unit.

Abstract: Provided is a semiconductor device package in which instability of a bonding wire that may occur when a plurality of semiconductor chips are stacked is prevented and which obtains a light, thin and small structure. The semiconductor device package includes a substrate having a plurality of substrate pads on a top surface of the semiconductor device package and includes a plurality of semiconductor chips stacked on the substrate. Each of the semiconductor chips have a chip pad electrically connected to a common pin, e.g., to which a common signal may be concurrently applied to each of the semiconductor chips. An interposer chip, also stacked on the substrate, has a connecting wire electrically connected to the chip pad, the common pin of each of the semiconductor chips being thereby electrically coupled at the connecting wire via the chip pad, and the connecting wire being thereby electrically connected to the substrate pad.

Abstract: A multi-chip package, a semiconductor device used therein, and manufacturing method thereof are provided. The multi-chip package may include a substrate having a plurality of substrate bonding pads formed on an upper surface thereof, at least one first semiconductor chip mounted on the substrate, and at least one second semiconductor chip mounted on the substrate where the at least one first semiconductor chip may be mounted. The at least one second semiconductor chip may include at least one three-dimensional space so as to allow the at least one first semiconductor chip to be enclosed within the at least one three-dimensional space. The at least one three-dimensional space may be a cavity, a groove, or a combination thereof.

Abstract: The present invention provides an aqueous formulation of human erythropoietin having the storage stability over a long period without serum albumin, in which the formulation comprises a pharmaceutically effective amount of human erythropoietin; non-ionic surfactant, polyhydric alcohol, neutral amino acid and sugar alcohol as stabilizers; isotonic reagent; and buffering reagent.

Abstract: Provided are a high-power ball grid array (BGA) and a method for manufacturing the high-power BGA. The high-power BGA includes a printed circuit board which has a through hole at its center, connection pads which are formed on the bottom of the printed circuit board, matrix solder balls which surround the through hole and are adjacent to the connection pads on the bottom of the printed circuit board, a heat spreader which is formed on the top surface of the printed circuit board and includes an insulating layer of a high thermal conductivity, a semiconductor chip which is mounted downwardly on the bottom surface of the heat spreader, within the through hole, and includes a plurality of pads for bonding via gold wires with the connection pad, and a passive film which fills the through hole and is formed at the bottom of the semiconductor chip.

Abstract: An apparatus for adjusting a height of a suction brush for use in a vacuum cleaner includes a height adjusting knob rotatably disposed in an inserting recess formed in the suction brush, and having an inclined part formed thereon, so that a height of the suction brush from a surface to be cleaned is varied as a position of the height adjusting knob rotated, a supporting member to support the suction brush in contact with the inclined part thus to allow the suction brush to be ascended and descended by the inclined part, and a passage disposed between an inner circumferential surface of the inserting recess and an outer circumferential surface of the height adjusting knob to pass fine dirt therethrough. With the passage, the fine dirt is not tied up between the inner circumferential surface of the inserting recess and the outer circumferential surface of the height adjusting knob. Accordingly, the rotation of the height adjusting knob is not restricted or obstructed due to the fine dirt.

Abstract: A high-power BGA includes a printed circuit board with a through hole, connection pads formed on the bottom of the printed circuit board, matrix solder balls surrounding the through hole and adjacent to the connection pads, a heat spreader on the top surface of the printed circuit board that includes an insulating layer of a high thermal conductivity, a semiconductor chip mounted within the through hole on the bottom surface of the heat spreader that includes a number of contact pads for bonding with the connection pads using gold wires, and a passive film filling the through hole and around the semiconductor chip. By interposing a ceramic insulating layer between the semiconductor chip and the heat spreader, charge generation between the semiconductor chip and the heat spreader is sharply reduced, and defects such as ESD (electrostatic discharge) is reduced during testing and mounting of the package.

Abstract: The present disclosure relates to a dust separating apparatus using a centrifugal force. The dust separating apparatus includes a cyclone body configured to separate dust from air using centrifugal force, and having an entering pipe through which the air enters; a dust collecting receptacle configured to be detachably connected to a bottom end of the cyclone body, and for collecting dust separated from the air; and a filter unit configured to be detachably disposed to the cyclone body, wherein the filter unit has a compact, at least double structure formed by a filter for filtering large dust and a filter for filtering fine dust.

Abstract: Embodiments of the invention provide a method for fabricating a system in package. In one embodiment, the method comprises preparing a printed circuit board (PCB) strip comprising a plurality of individual PCBs, stacking a plurality of first semiconductor chips and forming an encapsulant on a first surface of a first individual PCB of the plurality of individual PCBs to form a first semiconductor chip stack structure comprising a first semiconductor chip stack, and performing a first test adapted to test one of the first semiconductor chips in the first semiconductor chip stack. The method further comprises flip chip bonding a second semiconductor chip to a second surface of the first individual PCB if the first semiconductor chip stack structure meets a test standard based on a result of the first test, and dividing the first semiconductor chip stack structure to form a system in package.

Abstract: A wiring substrate having variously sized ball pads, a semiconductor package including the wiring substrate, and a stack package using the semiconductor package, to improve board level reliability (BLR) of a semiconductor package or stack package mounted on a mother board are shown. Outer ball pads are formed to have relatively greater surface areas at the corners of the semiconductor package as compared to those at other areas and are formed to have the greatest surface area within a designable range. Additionally, occurrence of cracks may be inhibited at junctions of other solder balls by forming dummy solder pads at the outermost corners among the outer ball pads formed proximate to the corners of the wiring substrate. Stress arising during a board level reliability test is absorbed without product failure at junctions between the dummy solder pads and dummy solder balls.