Abstract: A semiconductor package including a mounting substrate, a first semiconductor chip mounted on an upper surface of the mounting substrate, a unit package stacked on the first semiconductor chip may be provided. The unit package includes a package substrate and a second semiconductor chip mounted on the package substrate. A plurality of bonding wires connects bonding pads of the mounting substrate and connection pads of the unit package, thereby electrically connecting the first and second semiconductor chips to each other. A molding member is provided on the mounting substrate to cover the first semiconductor chip and the unit package.

Abstract: A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, and a plurality of connections electrically connecting the first and second semiconductor packages. The connections are disposed on an outer region of the first package substrate outside the first semiconductor chip. The connections are disposed along opposite first longer sides and opposite shorter second sides of the first package substrate. The heights of those connections disposed along each longer first side gradually vary from a central to an outer region (i.e., the ends) of the longer first side.

Abstract: A semiconductor chip and a first heat dissipation pattern are mounted on a substrate. The first heat dissipation pattern has an opening therein and exposes the semiconductor chip therethrough. A second heat dissipation pattern including a thermal interface material (TIM) is interposed between a side surface of the semiconductor chip and the first heat dissipation pattern.

Abstract: An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.

Abstract: Disclosed is a dynamic postural balance training system. The system includes: a base frame; a support frame which extends upwards from the base frame; a roll motion frame which is coupled to the upper portion of the support frame by a first shaft so as to be rotatable to the left or the right; a pitch motion frame which is coupled to the roll motion frame by a second shaft so as to be rotatable forwards or rearwards; a pelvis fastening unit which is disposed inside the pitch motion frame and which expands to fix the pelvis of the user in place; a connector which extends downwards from the pitch motion frame; and a foot fastening unit which is coupled to the lower end of the connector and expands to fix the feet of the user in place.

Abstract: A semiconductor device having a printed circuit board and a semiconductor chip. The printed circuit board includes a chip region, a plurality of first ball lands adjacent to the chip region, and at least one second ball land adjacent to the first ball lands. The semiconductor chip is mounted on the chip region. The first ball lands are arranged to have a first pitch. One of the first ball lands which is nearest to the second ball land, and the second ball land have a second pitch greater than the first pitch.

Abstract: Semiconductor packages are provided. The semiconductor packages may include an upper package including a plurality of upper semiconductor devices connected to an upper package substrate. The semiconductor packages may also include a lower package including a lower semiconductor device connected to a lower package substrate. The upper and lower packages may be connected to each other.

Abstract: A system for detecting and diagnosing a faultive state of an airplane engine, including: at least one vibration sensor attached to an airplane; a reference model database construction unit; and a fault detection and diagnosis unit which estimates a parameter of a model, obtains a test variable and a numerator coefficient value difference of a transfer function between the models, and the covariance of parameter estimation error, and diagnoses the faultive state and the faultive cause of the airplane engine. Accordingly, the present invention can determine the faultive state and the detective cause of the airplane engine using the vibration data of the airplane engine.

Abstract: A semiconductor device having a printed circuit board and a semiconductor chip. The printed circuit board includes a chip region, a plurality of first ball lands adjacent to the chip region, and at least one second ball land adjacent to the first ball lands. The semiconductor chip is mounted on the chip region. The first ball lands are arranged to have a first pitch. One of the first ball lands which is nearest to the second ball land, and the second ball land have a second pitch greater than the first pitch.

Abstract: A package stack structure may an upper package include an upper package substrate having a first edge and a second edge opposite to the first edge. The upper package substrate has a first region arranged near the first edge and a second region arranged near the second edge. A first upper semiconductor device is mounted on the upper package substrate. The package stack structure may also include a lower package having a lower package substrate and a lower semiconductor device. The lower package is connected to the upper package through a plurality of inter-package connectors. The plurality of the inter-package connectors may include first inter-package connectors configured to transmit data signals; second inter-package connectors configured to transmit address/control signals; third inter-package connectors configured to provide a supply voltage for an address/control circuit; and fourth inter-package connectors configured to provide a supply voltage for a data circuit.

Abstract: A semiconductor stack package apparatus includes an upper semiconductor package and a lower semiconductor package. The upper semiconductor chip includes a chip pad, an upper substrate including a substrate pad formed on a top surface of the upper substrate and an upper ball land formed on a bottom surface of the upper substrate and attached to an intermediate solder ball, and a wire connecting the chip pad and the substrate pad. The lower semiconductor package includes a lower semiconductor chip including a bump, and a lower substrate including a bump land formed on a top surface of the lower substrate in an area corresponding to the bump, an intermediate ball land formed on the top surface of the lower substrate in an area corresponding to the intermediate solder ball, and a lower ball land formed on a bottom surface of the lower substrate and attached to a lower solder ball.

Abstract: There is provided a probe card comprising a plurality of probe tips, each being ball-shaped or pillar-shaped and having a top end in contact with each of target chip pads to be tested; a first space converting unit; a second space converting unit; a frame configured to support the second space converting unit; an interposer unit; and a circuit board.

Abstract: A stack package includes a lower package including a lower package substrate and a lower semiconductor chip disposed on the lower package substrate, an upper package including an upper package substrate and an upper semiconductor chip disposed on the upper package substrate, a fastening element formed between a top surface of the lower semiconductor chip and a bottom surface of the upper package substrate, and a halogen-free inter-package connector connecting the lower package substrate to the upper package substrate.

Abstract: A data processing system includes a scalable encoder including an encoder and a control module. The encoder includes at least two layer encoders and has an encoder configuration determined during initialization. The control module is configured to generate an encoder control code in accordance with transmission conditions of a communication channel, the encoder control code controlling operation of the at least two encoding layers.

Abstract: A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, and a plurality of connections electrically connecting the first and second semiconductor packages. The connections are disposed on an outer region of the first package substrate outside the first semiconductor chip. The connections are disposed along opposite first longer sides and opposite shorter second sides of the first package substrate. The heights of those connections disposed along each longer first side gradually vary from a central to an outer region (i.e., the ends) of the longer first side.

Abstract: Provided is an early rehabilitation training system that increase the intensity of patient rehabilitation training to shorten the time it takes for patients to progress to a secondary rehabilitation training stage by allowing patients incapable of self-ambulation to be artificially rehabilitated in a prone, bed-ridden position. The system includes a treatment bed (2) configured with a mattress (2a), a base (2b) disposed below the mattress (2a) and coupled through a hinge to one end of the mattress (2a), and a tilting unit (2c) provided between the mattress (2a) and the base (2b) to adjust an upright angle of the mattress (2a); and a rotating unit (10) provided below the mattress (2a) of the treatment bed (2) to secure a patient's feet and provide artificial exercising of the patient's feet through gravity when the upright angle of the mattress (2a) is changed by the tilting unit (2c).

Abstract: An error concealment apparatus and method that can selectively use error concealment techniques according to an error occurrence rate is disclosed. The error concealment apparatus includes an error detection unit for detecting errors occurring in video frames, first and second error concealment units for concealing the detected errors, and a video output unit for selectively outputting the video frames of which the errors have been concealed by the first and second error concealment units according to the results of error detection.

Abstract: A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from a central region of the substrate body toward an outer edge of the substrate body based on a reflow soldering process warpage profile for the semiconductor package.

Abstract: A method and apparatus for encoding/decoding an image that divide an image sequence into sub-groups and determine encoding modes applied to bi-directional pictures included in each sub-group using correlations between the bi-directional pictures and reference pictures are provided. The image encoding method includes dividing a group of pictures (GOP) to be encoded according to consecutive B pictures into sub-groups; calculating the correlations between each B picture included in the sub-group and reference picture according to each encoding mode; and applying one of the encoding modes wherein the reference picture having the highest correlation with the B picture are used in each sub-group to encode the image, thereby improving encoding efficiency.

Abstract: A chip stack package may include a substrate, semiconductor chips, a molding member and a controller. The substrate may have a wiring pattern. The semiconductor chips may be stacked on a first surface of the substrate. Further, the semiconductor chips may be electrically connected to the wiring pattern. The molding member may be formed on the first substrate covering the semiconductor chips. The controller may be arranged on a second surface of the substrate. The controller may be electrically connected to the wiring pattern. The controller may have a selection function for selecting operable semiconductor chip(s) among the semiconductor chips.