Abstract: To stabilize video (an image sequence), reconstructed block data and decoding information of a video frame are received by unit of macroblock from a decoding circuit. Global affine parameters are determined and provided based on the reconstructed block data and the decoding information, and the global affine parameters represent an affine transform of a frame. Stabilized block data are provided based on the global affine parameters by compensating the reconstructed block data for an affine motion corresponding to the affine transform.

Abstract: A video/image compression method based on an region of interest (ROI) can be performed in a variable block video encoder such as a HEW. A ROI coding method using variable block size coding information partitions a maximum coding unit (LCU) block obtained from an image into coding unit (CU) blocks. To obtain a quantization parameter of each coding unit (CU) block, the value of its quantization parameter is assigned based on its first hierarchical depth information and its second hierarchical depth information by using the first hierarchical depth information related to the size of the coding unit (CU) block and using the second hierarchical depth information related to the size of a prediction unit (PU) block correspondingly represented in consequence of the partition of the coding unit (CU) block. The resulting values of a quantization parameter assigned to different coding unit (CU) blocks may be different.

Abstract: A semiconductor device having a printed circuit board and a semiconductor chip. The printed circuit board includes a chip region, a plurality of first ball lands adjacent to the chip region, and at least one second ball land adjacent to the first ball lands. The semiconductor chip is mounted on the chip region. The first ball lands are arranged to have a first pitch. One of the first ball lands which is nearest to the second ball land, and the second ball land have a second pitch greater than the first pitch.

Abstract: A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, and a plurality of connections electrically connecting the first and second semiconductor packages. The connections are disposed on an outer region of the first package substrate outside the first semiconductor chip. The connections are disposed along opposite first longer sides and opposite shorter second sides of the first package substrate. The heights of those connections disposed along each longer first side gradually vary from a central to an outer region (i.e., the ends) of the longer first side.

Abstract: A package stack structure may an upper package include an upper package substrate having a first edge and a second edge opposite to the first edge. The upper package substrate has a first region arranged near the first edge and a second region arranged near the second edge. A first upper semiconductor device is mounted on the upper package substrate. The package stack structure may also include a lower package having a lower package substrate and a lower semiconductor device. The lower package is connected to the upper package through a plurality of inter-package connectors. The plurality of the inter-package connectors may include first inter-package connectors configured to transmit data signals; second inter-package connectors configured to transmit address/control signals; third inter-package connectors configured to provide a supply voltage for an address/control circuit; and fourth inter-package connectors configured to provide a supply voltage for a data circuit.

Abstract: Semiconductor packages are provided. The semiconductor packages may include an upper package including a plurality of upper semiconductor devices connected to an upper package substrate. The semiconductor packages may also include a lower package including a lower semiconductor device connected to a lower package substrate. The upper and lower packages may be connected to each other.

Abstract: A semiconductor package having improved performance and reliability and a method of fabricating the same are provided. The semiconductor package includes a processing chip including a first pin at a first side to output a first signal, and a second pin at a second side to output a second signal different from the first signal, and a substrate having the processing chip thereon, the substrate including a first bump ball electrically connected to the first pin and a second bump ball electrically connected to the second pin, wherein the first bump ball and the second bump ball are adjacent at one of the first and second sides of the substrate.

Abstract: A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, and a plurality of connections electrically connecting the first and second semiconductor packages. The connections are disposed on an outer region of the first package substrate outside the first semiconductor chip. The connections are disposed along opposite first longer sides and opposite shorter second sides of the first package substrate. The heights of those connections disposed along each longer first side gradually vary from a central to an outer region (i.e., the ends) of the longer first side.

Abstract: Semiconductor packages are provided. The semiconductor packages may include an upper package including a plurality of upper semiconductor devices connected to an upper package substrate. The semiconductor packages may also include a lower package including a lower semiconductor device connected to a lower package substrate. The upper and lower packages may be connected to each other.

Abstract: A package stack structure may an upper package include an upper package substrate having a first edge and a second edge opposite to the first edge. The upper package substrate has a first region arranged near the first edge and a second region arranged near the second edge. A first upper semiconductor device is mounted on the upper package substrate. The package stack structure may also include a lower package having a lower package substrate and a lower semiconductor device. The lower package is connected to the upper package through a plurality of inter-package connectors. The plurality of the inter-package connectors may include first inter-package connectors configured to transmit data signals; second inter-package connectors configured to transmit address/control signals; third inter-package connectors configured to provide a supply voltage for an address/control circuit; and fourth inter-package connectors configured to provide a supply voltage for a data circuit.

Abstract: A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from a central region of the substrate body toward an outer edge of the substrate body based on a reflow soldering process warpage profile for the semiconductor package.

Abstract: A semiconductor package onto which a plurality of passive elements is mounted. A substrate includes a first surface and a second surface. A semiconductor chip is on one of the first surface and the second surface of the substrate. A plurality of passive elements are on the substrate. The plurality of passive elements include a plurality of first passive elements and a plurality of second passive elements that are taller than the plurality of first passive elements. The plurality of first passive elements are on at least one of the first surface and the second surface, and at least two of the plurality of second passive elements are on the second surface.

Abstract: A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, and a plurality of connections electrically connecting the first and second semiconductor packages. The connections are disposed on an outer region of the first package substrate outside the first semiconductor chip. The connections are disposed along opposite first longer sides and opposite shorter second sides of the first package substrate. The heights of those connections disposed along each longer first side gradually vary from a central to an outer region (i.e., the ends) of the longer first side.

Abstract: A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from a central region of the substrate body toward an outer edge of the substrate body based on a reflow soldering process warpage profile for the semiconductor package.

Abstract: A rate control method for multi-layered video coding, a video encoding apparatus and a video signal processing system employing the rate control method. In the rate control method for multi-layered video coding, encoding statistical information is generated based on the result of encoding input video data on a first layer. A second rate controller generates a plurality of quantization parameters to be used when encoding is performed on a second layer, based on the encoding statistical information and/or region of interest (ROI) information. Target numbers of bits that are to be respectively assigned to regions of a second layer are determined based on the encoding statistical information and/or ROI information, and the input video data is encoded at the second layer, based on the target numbers of bits.

Abstract: An air-conditioning control method for dividing an indoor space of a vehicle into a plurality of zones to perform individual air-conditioning for each zone, may include selecting boarding zones occupied by passengers from the plurality of zones, checking whether the number of the boarding zones occupied by the passengers may be one, correcting a detection temperature of an incar sensor into a temperature of the boarding zone using a mixing ratio of air for air-conditioning discharged from the corresponding boarding zone with air existing in the boarding zone when the number of the boarding zones occupied by the passengers may be one, and performing individual air-conditioning on the selected boarding zones by determining a target discharge temperature based on the corrected temperature of the boarding zone and using the determined target discharge temperature.

Abstract: A method of controlling power consumption of a portable device includes monitoring whether the portable device has connected to a docking station; and selecting and executing one of a plurality of power consumption controlling algorithms according to a monitoring result.

Abstract: An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.

Abstract: An operating method of an image capturing device includes capturing an image; detecting a target object from the captured image; calculating modification parameters based on the detected target object; generating an adjusted image by adjusting a size of an area of the captured image according to the modification parameters; and displaying the adjusted image.

Abstract: A bitrate estimation method includes: calculating a number of symbol bins of a received syntax element; deciding average bit amount corresponding to the number of symbol bins using a look-up table; and estimating a bitrate based on the number of symbol bins and the average bit amount. Bitrate estimation methods and corresponding devices have improved operation speed, accuracy and/or simplified computation.