Patents by Inventor Lang WANG

Lang WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Trench structure of semiconductor device having uneven nitrogen distribution liner
    Patent number: 9871100
    Abstract: A trench structure of a semiconductor device includes a substrate, an isolation structure, and a liner layer. The substrate has a trench therein. The isolation structure is disposed in the trench. The liner layer is disposed between the substrate and the isolation structure. The liner layer includes nitrogen, and the liner layer has spatially various nitrogen concentration.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: January 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Ming Lin, Shiu-Ko Jangjian, Chun-Che Lin, Ying-Lang Wang, Wei-Ken Lin, Chuan-Pu Liu
  • Semiconductor device and manufacturing method thereof
    Patent number: 9865731
    Abstract: A semiconductor device includes a p-type metal oxide semiconductor device (PMOS) and an n-type metal oxide semiconductor device (NMOS) disposed over a substrate. The PMOS has a first gate structure located on the substrate, a carbon doped n-type well disposed under the first gate structure, a first channel region disposed in the carbon doped n-type well, and activated first source/drain regions disposed on opposite sides of the first channel region. The NMOS has a second gate structure located on the substrate, a carbon doped p-type well disposed under the second gate structure, a second channel region disposed in the carbon doped p-type well, and activated second source/drain regions disposed on opposite sides of the second channel region.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: January 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: I-Chih Chen, Ying-Lang Wang, Chih-Mu Huang, Ying-Hao Chen, Wen-Chang Kuo, Jung-Chi Jeng
  • Method for producing alpha-glucosidase inhibitors utilizing sp
    Patent number: 9850519
    Abstract: A method for producing alpha-glucosidase inhibitors utilizing Paenibacillus sp., wherein utilizing a Paenibacillus sp. strain which is deposited at Deutsche Sammlung von Mikroorganismen and Zellkulturen GmbH (DSMZ) and numbered No. DSM 32521 to produce the alpha-glucosidase inhibitors, the Paenibacillus sp. Strain is cultivated in a commercial culture medium or a shrimp/crab residue-contained culture medium, and the alpha-glucosidase inhibitors is separated from a fermented supernatant. The alpha-glucosidase inhibitors have strong inhibitory activity.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: December 26, 2017
    Assignee: TAMKANG UNIVERSITY
    Inventors: San-Lang Wang, Yao-Haur Kuo, Po-Hao Shih, Van-Bon Nguyen, Anh-Dzung Nguyen
  • Methods and apparatus for resistive random access memory (RRAM)
    Patent number: 9847478
    Abstract: Methods and apparatuses for a resistive random access memory (RRAM) device are disclosed. The RRAM device comprises a bottom electrode, a resistive switching layer disposed on the bottom electrode, and a top electrode disposed on the resistive switching layer. The resistive switching layer is made of a composite of a metal, Si, and O. There may be an additional tunnel barrier layer between the top electrode and the bottom electrode. The top electrode and the bottom electrode may comprise multiple sub-layers.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: December 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Chang Chang, Yong-En Syu, Fu-Yen Jian, Shih-Chieh Chang, Ying-Lang Wang
  • APPARATUS AND METHOD FOR TREATING WAFER
    Publication number: 20170352574
    Abstract: An apparatus for treating a wafer is provided. The apparatus includes a platen, a chamber, an etch gas supplier and a tilting mechanism. The chamber has at least one aperture at least partially facing to the platen. The etch gas supplier is fluidly connected to the chamber. The tilting mechanism is coupled with the platen for allowing the platen to have at least one first degree of freedom to tilt relative to the aperture of the chamber.
    Type: Application
    Filed: June 2, 2016
    Publication date: December 7, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kei-Wei CHEN, Chun-Hsiung TSAI, Huai-Tei YANG, Shiu-Ko JANGJIAN, Ying-Lang WANG, Ziwei FANG
  • Lithography tool with backside polisher
    Patent number: 9829806
    Abstract: Methods for processing a substrate having a structure formed thereon and a system for processing a substrate are provided. A substrate is received from first processing equipment, where the first processing equipment has formed the structure on the substrate. A lithography process is performed on the received substrate. The lithography process includes exposing the substrate under an optical condition. The lithography process further includes polishing a backside of the substrate prior to the exposing of the substrate, where the polishing is configured to remove a topographical feature of the backside of the substrate or to remove a contaminant from the backside of the substrate. The substrate does not undergo a cleaning procedure during a period of time between i) the forming of the structure on the substrate, and ii) the exposing of the substrate.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: November 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Huai-Tei Yang, Ying-Lang Wang
  • Block Layer in the Metal Gate of MOS Devices
    Publication number: 20170323940
    Abstract: A method includes method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer, removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess and over the gate dielectric layer. The metal layer has an n-work function. A block layer is deposited over the metal layer using Atomic Layer Deposition (ALD). The remaining portion of the recess is filled with metallic materials, wherein the metallic materials are overlying the metal layer.
    Type: Application
    Filed: July 21, 2017
    Publication date: November 9, 2017
    Inventors: Jung-Chih Tsao, Chi-Cheng Hung, Yu-Sheng Wang, Wen-Hsi Lee, Kei-Wei Chen, Ying-Lang Wang
  • Semiconductor device and fabricating method thereof
    Patent number: 9812569
    Abstract: A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate; a source/drain region having a first dopant in the substrate; a barrier layer having a second dopant formed around the source/drain region in the substrate. When a semiconductor device is scaled down, the doped profile in source/drain regions might affect the threshold voltage uniformity, the provided semiconductor device may improve the threshold voltage uniformity by the barrier layer to control the doped profile.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: November 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Chih Chen, Ying-Lang Wang, Chih-Mu Huang, Ying-Hao Chen, Wen-Chang Kuo, Jung-Chi Jeng
  • Metal shield structure and methods for BSI image sensors
    Patent number: 9812492
    Abstract: A backside illumination image sensor structure comprises an image sensor formed adjacent to a first side of a semiconductor substrate, wherein an interconnect layer is formed over the first side of the semiconductor substrate, a backside illumination film formed over a second side of the semiconductor substrate, a metal shielding layer formed over the backside illumination film and a via embedded in the backside illumination film and coupled between the metal shielding layer and the semiconductor substrate.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: November 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Chi-Cherng Jeng, Volume Chien, Ying-Lang Wang
  • SEMICONDUCTOR DEVICE HAVING BARRIER LAYER TO PREVENT IMPURITY DIFFUSION
    Publication number: 20170317164
    Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type region including a first conductivity type impurity. A first gate structure is on the semiconductor substrate overlying the first conductivity type region. A second conductivity type region including a second conductivity type impurity is formed in the semiconductor substrate. A barrier layer is located between the first conductivity type region and the second conductivity type region. The barrier layer prevents diffusion of the second conductivity type impurity from the second conductivity type region into the first conductivity type region.
    Type: Application
    Filed: July 17, 2017
    Publication date: November 2, 2017
    Inventors: I-Chih CHEN, Chih-Mu HUANG, Fu-Tsun TSAI, Meng-Yi WU, Yung-Fa LEE, Ying-Lang WANG
  • FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20170250281
    Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, first spacers, second spacers and source and drain regions is described. The substrate has fins and insulators disposed between the fins. The at least one gate structure is disposed over the fins and disposed on the insulators. The first spacers are disposed on opposite sidewalls of the at least one gate structure. The source and drain regions are disposed on two opposite sides of the at least one gate structure and beside the first spacers. The second spacers are disposed on the two opposite sides of the at least one gate structure and beside the first spacers. The source and drain regions are sandwiched between the opposite second spacers.
    Type: Application
    Filed: February 25, 2016
    Publication date: August 31, 2017
    Inventors: Chun Hsiung Tsai, Ziwei Fang, Shiu-Ko JangJian, Kei-Wei Chen, Huai-Tei Yang, Ying-Lang Wang
  • Block layer in the metal gate of MOS devices
    Patent number: 9735231
    Abstract: A method includes method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer, removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess and over the gate dielectric layer. The metal layer has an n-work function. A block layer is deposited over the metal layer using Atomic Layer Deposition (ALD). The remaining portion of the recess is filled with metallic materials, wherein the metallic materials are overlying the metal layer.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Chih Tsao, Chi-Cheng Hung, Yu-Sheng Wang, Wen-Hsi Lee, Kei-Wei Chen, Ying-Lang Wang
  • Semiconductor device
    Patent number: 9735271
    Abstract: A semiconductor device includes an isolation feature in a substrate. The semiconductor device further includes a first source/drain feature in the substrate, wherein a first side of the first source/drain feature contacts the isolation feature, and the first source/drain feature exposes a portion of the isolation feature below a top surface of the substrate. The semiconductor device further includes a silicide layer over the first source/drain feature. The semiconductor device further includes a dielectric layer along the exposed portion of the isolation feature below the top surface of the substrate, wherein the dielectric layer contacts the silicide layer. The semiconductor device further includes a second source/drain feature in the substrate on an opposite side of a gate stack from the first source/drain feature, wherein the second source/drain feature has a substantially uniform thickness.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: August 15, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen Chu Hsiao, Lai Wan Chong, Chun-Chieh Wang, Ying Min Chou, Hsiang Hsiang Ko, Ying-Lang Wang
  • Semiconductor wafer and semiconductor die
    Patent number: 9728511
    Abstract: A semiconductor wafer includes a substrate, an integrated circuit and a die seal ring structure. The substrate is with a die region, a die seal ring region surrounding the die region and a scribe line region surrounding the die seal ring region. The substrate includes a first surface and a second surface opposite to the first surface, and periodic recesses within the first surface of the die seal ring region, the scribe line region or both the die seal ring region and the scribe line region. The integrated circuit is located on the first surface and the second surface of the die region. The die seal ring structure is located on the second surface of the die seal ring region. A semiconductor die is also provided.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: August 8, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsi-Jung Wu, Volume Chien, Ying-Lang Wang, Hsin-Chi Chen, Ying-Hao Chen, Hung-Ta Huang
  • Semiconductor device having barrier layer to prevent impurity diffusion
    Patent number: 9728598
    Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type region including a first conductivity type impurity. A first gate structure is on the semiconductor substrate overlying the first conductivity type region. A second conductivity type region including a second conductivity type impurity is formed in the semiconductor substrate. A barrier layer is located between the first conductivity type region and the second conductivity type region. The barrier layer prevents diffusion of the second conductivity type impurity from the second conductivity type region into the first conductivity type region.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: August 8, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Chih Chen, Chih-Mu Huang, Fu-Tsun Tsai, Meng-Yi Wu, Yung-Fa Lee, Ying-Lang Wang
  • Image sensor manufacturing methods
    Patent number: 9721984
    Abstract: Semiconductor devices and back side illumination (BSI) sensor manufacturing methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece and forming an integrated circuit on a front side of the workpiece. A grid of a conductive material is formed on a back side of the workpiece using a damascene process.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: August 1, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mu-Han Cheng, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang
  • Metal Shielding Layer in Backside Illumination Image Sensor Chips and Methods for Forming the Same
    Publication number: 20170213861
    Abstract: A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed at a surface of the semiconductor substrate, wherein the photo-sensitive device is configured to receive a light signal from the backside of the semiconductor substrate, and convert the light signal to an electrical signal. An amorphous-like adhesion layer is disposed on the backside of the semiconductor substrate. The amorphous-like adhesion layer includes a compound of nitrogen and a metal. A metal shielding layer is disposed on the backside of the semiconductor substrate and contacting the amorphous-like adhesion layer.
    Type: Application
    Filed: April 10, 2017
    Publication date: July 27, 2017
    Inventors: Shih-Chieh Chang, Jian-Shin Tsai, Chih-Chang Huang, Ing-Ju Lee, Ching-Yao Sun, Jyun-Ru Wu, Ching-Che Huang, Szu-An Wu, Ying-Lang Wang
  • Algorithmic Approach for Determining the Plasma Genome Abnormality PGA and the Urine genome abnormality UGA scores based on Cell Free cfDNA Copy Number Variations in Plasma and Urine.
    Publication number: 20170211153
    Abstract: The present invention relates to methods of using cell-free DNA analysis for guiding treatment of advanced prostate cancer. In particular, liquid biopsies are collected from urine and/or plasma of patients for measuring copy number variation in cell-free DNA associated with metastatic prostate cancer. In particular, urine genomic abnormality (UGA) and plasma genomic abnormality (PGA) values are contemplated for use in predicting treatment responses in advanced prostate cancer patients and for use in making decisions related to androgen deprivation therapy (ADT) treatment outcomes in hormone sensitive stage and for starting or changing chemotherapy treatments in castrate resistant advanced cancer stage.
    Type: Application
    Filed: January 20, 2017
    Publication date: July 27, 2017
    Inventors: Manish Kohli, Lang Wang, Chiang-Ching Huang
  • Wafer edge trim blade with slots
    Patent number: 9676114
    Abstract: A wafer edge trim blade includes a round blade body and at least one slot formed inward from an outside edge of the round blade body. The at least one slot is configured to remove debris generated during wafer edge trimming using the wafer edge trim blade.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: June 13, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Ting Kuo, Kei-Wei Chen, Ying-Lang Wang, Kuo-Hsiu Wei
  • Semiconductor devices utilizing partially doped stressor film portions
    Patent number: 9634119
    Abstract: A method includes providing a gate structure over a semiconductor substrate and forming a source/drain region associated with the gate structure by etching an opening in the semiconductor substrate, performing a first epitaxial growth process while an entirety of a sidewall of the opening is exposed to grow a first epitaxy material in the opening. The first epitaxial growth process is free of a first dopant impurity. A second epitaxial growth process is performed after first epitaxial growth process to grow a second epitaxy material on the first epitaxy material. The second epitaxy material has the first dopant impurity at a first concentration. Further, a third epitaxial growth process is performed after the second epitaxial growth process that includes introducing the first dopant impurity at a second concentration, the second concentration greater than the first concentration.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: April 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen Chu Hsiao, Ju Wen Hsiao, Ying Min Chou, Hsiang Hsiang Ko, Ying-Lang Wang