Abstract: A method for fabricating a semiconductor device includes forming one or more layers including at least one of a liner and a barrier along surfaces of a first interlevel dielectric (ILD) layer within a trench, after forming the one or more liners, performing a via etch to form a via opening exposing a first conductive line corresponding to a first metallization level, and forming, within the via opening and on the first conductive line, a barrier-less prefilled via including first conductive material.

Abstract: A technique relates to an integrated circuit. A first dielectric material is formed on a layer, and a second dielectric material is formed on the first dielectric material, the second dielectric material having a different characteristic than the first dielectric material. Conductive material is formed in the first dielectric material, the second dielectric material, and the layer, the conductive material forming interconnects in the layer separated by a stack of the first dielectric material and the second dielectric material. The conductive material forms a self-aligned conductive via on one of the interconnects according to a topography of the stack, the stack of the first dielectric material and the second dielectric material electrically insulating the one of the interconnects from another one of the interconnects.

Abstract: A semiconductor structure includes a plurality of field effect transistors formed on a substrate including p-type doped field effect transistors (pFETs) and n-type doped field effect transistors (nFETs). A self-aligned buried local interconnect electrically connects a bottom source or drain region of the pFET with an adjacent bottom source or drain region of the nFET. The self-aligned buried local interconnect is serially aligned with and intermediate opposing ends of a gate electrode. Other embodiments include methods for forming the buried local interconnect.

Abstract: A semiconductor device and method of making the same, wherein in accordance with an embodiment of the present invention, the device includes a first conductive line including a first conductive material, and a second conductive line including a second conductive material. A via connects the first conductive line to the second conductive line, wherein the via includes conductive via material, wherein the via material top surface is coated with a liner material, wherein the via is a bottomless via.

Abstract: Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having a conductive thin metal layer on a top via that promotes the selective growth of the next level interconnect lines (the line above). In a non-limiting embodiment of the invention, a first conductive line is formed in a dielectric layer. A via is formed on the first conductive line and a seed layer is formed on the via and the dielectric layer. A surface of the seed layer is exposed and a second conductive line is deposited onto the exposed surface of the seed layer. In a non-limiting embodiment of the invention, the second conductive line is selectively grown from the seed layer.

Abstract: The present invention may receive a plurality of unlock instructions based on determining a location is secured from access by the drone. The present invention may use the plurality of received unlock instructions to access the location with an access device while determining the drone is present at the drop off location. The present invention may use the plurality of received unlock instructions to re-secure the location with the access device when determining successful delivery of a package by the drone, and may monitor a security of the location.

Abstract: Embodiments of the present invention are directed to fabrication methods and resulting structures for subtractively forming a top via using a hybrid metallization scheme. In a non-limiting embodiment of the invention, a surface of a conductive line is recessed below a topmost surface of a first liner layer. The first liner layer can be positioned between the conductive line and a dielectric layer. A top via layer is formed on the recessed surface of the conductive line and a hard mask is formed over a first portion of the top via layer. A second portion of the top via layer is removed. The remaining first portion of the top via layer defines the top via. The conductive line can include copper while the top via layers can include ruthenium or cobalt.

Abstract: A phase change memory device is provided. The phase change memory device includes a phase change memory material within an electrically insulating wall, a first heater terminal in the electrically insulating wall, and two read terminals in the electrically insulating wall.

Abstract: A method of forming a phase change memory device is provided. The method includes forming a spacer layer on a substrate, and forming a heater terminal contact in the spacer layer. The method further includes forming a liner layer on the heater terminal contact and the spacer layer, and forming a heater terminal in electrical contact with the heater terminal contact in the liner layer. The method further includes forming a conductive projection segment on the heater terminal. The method further includes forming a phase change material layer on the conductive projection segment, and forming a phase change material terminal on the phase change material layer, wherein an electrical current can pass between the heater terminal and the phase change material terminal through the phase change material layer.

Abstract: A multilayered integrated circuit includes a first layer with a first conductive element overlaying a substrate, a second layer with a second conductive element overlaying the first layer, an intermediate layer between the first layer and the second layer, and a via structure. The via structure is partially embedded within the intermediate layer and is communicatively coupled to the first conductive element and the second conductive element. The via structure extends from the first conductive element and has a first end with a first end width and a second end with a second end width. The second end is further from the substrate than the first end and the first end width is greater than the second end width such that the via structure tapers between the first end and the second end of the via structure.

Abstract: A multi-chip package structure includes a package substrate, an interconnect bridge device, first and second integrated circuit chips, and a connection structure. The first integrated circuit chip is flip-chip attached to at least the interconnect bridge device. The second integrated circuit chip is flip-chip attached to the interconnect bridge device and to the package substrate. The interconnect bridge device includes (i) wiring that is configured to provide chip-to-chip connections between the first and second integrated circuit chips and (ii) an embedded power distribution network that is configured to distribute at least one of a positive power supply voltage and a negative power supply voltage to at least one of the first and second integrated circuit chips attached to the interconnect bridge device. The connection structure (e.g., wire bond, injection molded solder, etc.) connects the embedded power distribution network to a power supply voltage contact of the package substrate.

Abstract: A multiterminal non-volatile memory cross-bar array system includes a set of conductive row rails, a set of conductive column rails configured to form a plurality of crosspoints at intersections between the conductive rails and the conductive column rails and a resistive processing unit at each of the crosspoints each representing a neuron in a neural network. At least one given conductive row rail includes first and second row lines is in contact with a given resistive processing unit. At least one given conductive column rail including first and second column lines is in contact with the given resistive processing unit.

Abstract: Three-dimensional positional spatial olfaction for virtual marketing associates a product with a product location within a virtual reality environment and identifies a product aroma associated with the product. A distance and a direction from the product location to a positional presence of a participant within the virtual reality environment is determined, and the product aroma is delivered to the participant in accordance with the distance and the direction. Delivery of the product aroma to the participant in accordance with the distance and the direction is used to lead the participant through the virtual reality environment to the product location where an interface for obtaining a physical copy of the product is displayed to the participant.

Abstract: Power distribution fabrics and methods of forming the same include forming a first layer of parallel conductive lines, having a first width. At least one additional layer of conductive lines is formed over the first layer of conductive lines, with the conductive lines of each successive layer in the at least one additional layer having a different orientation and a different width relative to the conductive lines of the preceding layer.

Abstract: A method for fabricating a semiconductor device including a self-aligned top via includes subtractively etching a conductive layer to form at least a first conductive line on a substrate. After the subtractive etching, the method further includes forming a barrier layer along the substate and along the first conductive line, planarizing at least portions of the barrier layer to obtain at least an exposed first conductive line, recessing at least the exposed first conductive line to form a first recessed conductive line, and forming conductive material in a via opening on the first recessed conductive line.

Abstract: A method for fabricating a semiconductor device including a skip via connection between metallization levels includes subtractively etching first conductive material to form a first via and a skip via on a first conductive line. The first via and the first conductive line are included within a first metallization level. The skip via is used to connect the first metallization level to a third metallization level above a second metallization level. The method further includes forming, on the first via from second conductive material, a second via disposed on a second conductive line. The second via and the second conductive line are included within the second metallization level.

Abstract: A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.

Abstract: A technique relates to an integrated circuit. A first dielectric material is formed on a layer, and a second dielectric material is formed on the first dielectric material, the second dielectric material having a different characteristic than the first dielectric material. Conductive material is formed in the first dielectric material, the second dielectric material, and the layer, the conductive material forming interconnects in the layer separated by a stack of the first dielectric material and the second dielectric material. The conductive material forms a self-aligned conductive via on one of the interconnects according to a topography of the stack, the stack of the first dielectric material and the second dielectric material electrically insulating the one of the interconnects from another one of the interconnects.

Abstract: Techniques are provided for constructing multi-chip package structures using pre-positioned interconnect bridge devices that are fabricated on a bridge wafer. For example, integrated circuit chips are mounted to a bridge wafer which is formed to have a plurality of pre-positioned interconnect bridge devices, wherein at least two integrated circuit chips are joined to each interconnect bridge device, and wherein each interconnect bridge device includes wiring to provide chip-to-chip connections between the integrated circuit chips connected to the interconnect bridge device. A wafer-level molding layer is formed on the bridge wafer to encapsulate the integrated circuit chips mounted to the bridge wafer. The interconnect bridge devices are released from the bridge wafer. The wafer-level molding layer is then diced to form a plurality of individual multi-chip modules.

Abstract: A method of increasing the surface area of a contact to an electrical device that in one embodiment includes forming a contact stud extending through an intralevel dielectric layer to a component of the electrical device, and selectively forming a contact region on the contact stud. The selectively formed contact region has an exterior surface defined by a curvature and has a surface area that is greater than a surface area of the contact stud. An interlevel dielectric layer is formed on the intralevel dielectric layer, wherein an interlevel contact extends through the interlevel dielectric layer into direct contact with the selectively formed contact region.