Patents by Inventor Lawrence A. Clevenger

Lawrence A. Clevenger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • TOP VIA WITH DAMASCENE LINE AND VIA
    Publication number: 20220005732
    Abstract: A method of forming a top via is provided. The method includes forming a sacrificial trench layer and conductive trench plug in an interlayer dielectric (ILD) layer on a conductive line. The method further includes forming a cover layer on the ILD layer, sacrificial trench layer, and conductive trench plug, and forming a sacrificial channel layer and a conductive channel plug on the conductive trench plug. The method further includes removing the cover layer and the ILD layer to expose the sacrificial trench layer and the sacrificial channel layer. The method further includes removing the sacrificial trench layer and the sacrificial channel layer, and forming a barrier layer on the conductive channel plug and conductive trench plug.
    Type: Application
    Filed: September 20, 2021
    Publication date: January 6, 2022
    Inventors: Lawrence A. Clevenger, Brent Anderson, Kisik Choi, Nicholas Anthony Lanzillo, Christopher J. Penny, Robert Robison
  • ETCH STOP LAYER REMOVAL FOR CAPACITANCE REDUCTION IN DAMASCENE TOP VIA INTEGRATION
    Publication number: 20220005731
    Abstract: A method of forming an interconnect structure includes forming at least one second-level interconnect in a sacrificial dielectric layer that is formed on an upper surface of a sacrificial etch stop layer, and removing the sacrificial dielectric layer and the sacrificial etch stop layer while maintaining the at least one second-level interconnect so as to expose an underlying dielectric layer. The method further includes depositing a replacement dielectric layer on an upper surface of the underlying dielectric layer to embed the at least one second-level interconnect in the replacement dielectric layer. Accordingly, an interconnect structure can be formed that includes one or more first-level interconnect in a dielectric layer and one or more second-level interconnects in a replacement dielectric layer stacked on the dielectric layer. The replacement dielectric layer directly contacts the dielectric layer.
    Type: Application
    Filed: September 20, 2021
    Publication date: January 6, 2022
    Inventors: Christopher J. Penny, Brent Anderson, Lawrence A. Clevenger, Robert Robison, Kisik Choi, Nicholas Anthony Lanzillo
  • TOP VIA WITH NEXT LEVEL LINE SELECTIVE GROWTH
    Publication number: 20220005761
    Abstract: Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having a conductive thin metal layer on a top via that promotes the selective growth of the next level interconnect lines (the line above). In a non-limiting embodiment of the invention, a first conductive line is formed in a dielectric layer. A via is formed on the first conductive line and a seed layer is formed on the via and the dielectric layer. A surface of the seed layer is exposed and a second conductive line is deposited onto the exposed surface of the seed layer. In a non-limiting embodiment of the invention, the second conductive line is selectively grown from the seed layer.
    Type: Application
    Filed: September 15, 2021
    Publication date: January 6, 2022
    Inventors: Brent Anderson, Lawrence A. Clevenger, Christopher J. Penny, Nicholas Anthony Lanzillo, Kisik Choi, Robert ROBISON
  • Fully aligned top vias
    Patent number: 11217481
    Abstract: A method of forming fully aligned top vias is provided. The method includes forming a fill layer on a conductive line, wherein the fill layer is adjacent to one or more vias. The method further includes forming a spacer layer selectively on the exposed surface of the fill layer, wherein the top surface of the one or more vias is exposed after forming the spacer layer. The method further includes depositing an etch-stop layer on the exposed surfaces of the spacer layer and the one or more vias, and forming a cover layer on the etch-stop layer.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: January 4, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicholas Anthony Lanzillo, Koichi Motoyama, Somnath Ghosh, Christopher J. Penny, Robert Robison, Lawrence A. Clevenger
  • Behavior-based interactive educational sessions
    Patent number: 11210968
    Abstract: A computer system interacts with a user with a behavioral state. An activity performed by an entity with a behavioral state is determined. A virtual character corresponding to the entity and performing the determined activity of the entity is generated and displayed. A mental state of the entity responsive to the virtual character is detected. In response to detection of a positive mental state of the entity, one or more natural language terms are provided to the entity corresponding to the activity performed by the virtual character. Embodiments of the present invention further include a method and program product for interacting with a user with a behavioral state in substantially the same manner described above.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: December 28, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Stefania Axo, Leigh Anne H. Clevenger, Krishna R. Tunga, Mahmoud Amin, Bryan Gury, Christopher J. Penny, Mark C. Wallen, Zhenxing Bi, Yang Liu
  • Machine learning enhanced optical-based screening for in-line wafer testing
    Patent number: 11199505
    Abstract: A method for machine learning enhanced optical-based screening for in-line wafer testing includes receiving optical spectra data for a wafer-under-test by performing scatterometry on the wafer-under-test, performing predictive model screening by applying a predictive model based on the optical spectra data, determining whether a device associated with the wafer-under-test is defective based on the predictive model screening, and if the device is determined to be defective, dynamically modifying a yield map associated with the wafer-under-test, including reassigning at least one die.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: December 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Robin Hsin Kuo Chao, Mary Breton, Huai Huang, Dexin Kong, Lawrence A. Clevenger
  • WELL-CONTROLLED EDGE-TO-EDGE SPACING BETWEEN ADJACENT INTERCONNECTS
    Publication number: 20210384123
    Abstract: Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a first dielectric layer. A first interconnect is formed in the first dielectric layer and includes a first top surface, a first bottom surface, and a first sidewall extending from an edge of the first top surface to an edge of the first bottom surface. A second interconnect is formed in the first dielectric layer and includes a second top surface, a second bottom surface, and a second sidewall extending from an edge of the second top surface to an edge of the second bottom surface. A spacing from the edge of the first top surface to the edge of the second top surface is greater than a spacing from the edge of the first bottom surface to the edge of the second bottom surface.
    Type: Application
    Filed: June 3, 2020
    Publication date: December 9, 2021
    Inventors: Brent Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi, Robert Robison
  • Well-controlled edge-to-edge spacing between adjacent interconnects
    Patent number: 11195795
    Abstract: Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a first dielectric layer. A first interconnect is formed in the first dielectric layer and includes a first top surface, a first bottom surface, and a first sidewall extending from an edge of the first top surface to an edge of the first bottom surface. A second interconnect is formed in the first dielectric layer and includes a second top surface, a second bottom surface, and a second sidewall extending from an edge of the second top surface to an edge of the second bottom surface. A spacing from the edge of the first top surface to the edge of the second top surface is greater than a spacing from the edge of the first bottom surface to the edge of the second bottom surface.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: December 7, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi, Robert Robison
  • Encapsulation topography-assisted self-aligned MRAM top contact
    Patent number: 11195993
    Abstract: Encapsulation topography-assisted techniques for forming self-aligned top contacts in MRAM devices are provided. In one aspect, a method for forming an MRAM device includes: forming MTJs on interconnects embedded in a first dielectric; depositing an encapsulation layer over the MTJs; burying the MTJs in a second dielectric; patterning a trench in the second dielectric over the MTJs exposing the encapsulation layer over tops of the MTJs which creates a topography at the trench bottom; forming a metal line in the trench over the topography; recessing the metal line which breaks up the metal line into segments separated by exposed peaks of the encapsulation layer; recessing the exposed peaks of the encapsulation layer to form recesses at the tops of the MTJs; and forming self-aligned contacts in the recesses. An MRAM device is also provided.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: December 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Michael Rizzolo, Nicholas Anthony Lanzillo, Benjamin D. Briggs, Lawrence A. Clevenger
  • Top via stack
    Patent number: 11195792
    Abstract: A semiconductor structure includes a first metallization layer disposed on a first etch stop layer. The first metallization layer includes a first conductive line and a second conductive line disposed in a first dielectric layer. The height of the first conductive line is greater than a height of the second conductive line. The semiconductor structure further includes a first via layer having a second dielectric layer disposed on a top surface of the first metallization layer and a first via in the second dielectric layer. The first via is configured to expose a portion of a top surface of the second conductive line. The semiconductor structure further includes a first conductive material disposed in the first via.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: December 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Brent Alan Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo, Robert Robison
  • Tight pitch via structures enabled by orthogonal and non-orthogonal merged vias
    Patent number: 11189566
    Abstract: In accordance with an embodiment of the present invention, a photolithographic mask is provided. The photolithographic mask includes at least one merged via pattern in the photolithographic mask for printing a merged via opening in a resist layer, wherein the at least one merged via pattern includes a compound shape having a first rectangular opening portion and a second rectangular opening portion that intersect at an angle.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: November 30, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dongbing Shao, Lawrence A. Clevenger, Shyng-Tsong Chen, Hao Tang, Jing Sha
  • Internet of things (IOT) real-time response to defined symptoms
    Patent number: 11185658
    Abstract: Systems, computer-implemented methods and/or computer program products that facilitate real-time response to defined symptoms are provided. In one embodiment, a computer-implemented method comprises: monitoring, by a system operatively coupled to a processor, a state of an entity; detecting, by the system, defined symptoms of the entity by analyzing the state of the entity; and transmitting, by the system, a signal that causes audio response or a haptic response to be provided to the entity, wherein transmission of the signal that causes the audio response or the haptic response is based on detection of the defined symptoms.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: November 30, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mahmoud Amin, Krishna R. Tunga, Lawrence A. Clevenger, Zhenxing Bi, Leigh Anne H. Clevenger
  • Top via interconnect having a line with a reduced bottom dimension
    Patent number: 11189568
    Abstract: A technique relates to an integrated circuit (IC). The IC includes a conductive line formed on a conductive via, the conductive line being formed though a dielectric material. The IC includes an etch stop layer having one or more extended portions intervening between one or more edge portions of the conductive line and the conductive via, the one or more edge portions being at a periphery of the conductive line and the conductive via, the etch stop layer including a higher dielectric breakdown than the dielectric material. The one or more extended portions of the etch stop layer cause the conductive line to be formed with a bottom part having a reduced dimension than an upper part of the conductive line.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: November 30, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi, Robert Robison
  • Cognitive system for automatic risk assessment, solution identification, and action enablement
    Patent number: 11182722
    Abstract: A method includes monitoring with at least one monitoring tool one or more activities associated with an enterprise. The method further includes analyzing data input from the at least one monitoring tool of the one or more activities, and determining, based on analytics performed on the data input and an implemented policy, when the one or more activities qualifies as an incident. A remedial response responsive to the incident is initiated. The monitoring, analyzing, determining and initiating steps are performed by at least one processing device including a processor operatively coupled to a memory.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: November 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alex Richard Hubbard, Spyridon Skordas, Marc A. Bergendahl, Cody John Murray, Gauri Karve, Lawrence A. Clevenger
  • Etch stop layer removal for capacitance reduction in damascene top via integration
    Patent number: 11177166
    Abstract: A method of forming an interconnect structure includes forming at least one second-level interconnect in a sacrificial dielectric layer that is formed on an upper surface of a sacrificial etch stop layer, and removing the sacrificial dielectric layer and the sacrificial etch stop layer while maintaining the at least one second-level interconnect so as to expose an underlying dielectric layer. The method further includes depositing a replacement dielectric layer on an upper surface of the underlying dielectric layer to embed the at least one second-level interconnect in the replacement dielectric layer. Accordingly, an interconnect structure can be formed that includes one or more first-level interconnect in a dielectric layer and one or more second-level interconnects in a replacement dielectric layer stacked on the dielectric layer. The replacement dielectric layer directly contacts the dielectric layer.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: November 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher J. Penny, Brent Anderson, Lawrence A. Clevenger, Robert Robison, Kisik Choi, Nicholas Anthony Lanzillo
  • Direct bonded heterogeneous integration packaging structures
    Patent number: 11177217
    Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: November 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kamal K. Sikka, Jon A. Casey, Joshua Rubin, Arvind Kumar, Dinesh Gupta, Charles L. Arvin, Mark W. Kapfhammer, Steve Ostrander, Maryse Cournoyer, Valérie A. Oberson, Lawrence A. Clevenger
  • Trapezoidal interconnect at tight BEOL pitch
    Patent number: 11177162
    Abstract: Techniques for forming trapezoidal-shaped interconnects are provided. In one aspect, a method for forming an interconnect structure includes: patterning a trench(es) in a dielectric having a V-shaped profile with a rounded bottom; depositing a liner into the trench(es) using PVD which opens-up the trench(es) creating a trapezoidal-shaped profile in the trench(es); removing the liner from the trench(es) selective to the dielectric whereby, following the removing, the trench(es) having the trapezoidal-shaped profile remains in the dielectric; depositing a conformal barrier layer into and lining the trench(es) having the trapezoidal-shaped profile; depositing a conductor into and filling the trench(es) having the trapezoidal-shaped profile over the conformal barrier layer; and polishing the conductor and the conformal barrier layer down to the dielectric. An interconnect structure is also provided.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: November 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Nicholas Anthony Lanzillo, Hosadurga Shobha, Huai Huang, Junli Wang, Koichi Motoyama, Christopher J. Penny, Lawrence A. Clevenger
  • Metalization repair in semiconductor wafers
    Patent number: 11171064
    Abstract: Embodiments are directed to a method for repairing features of a host semiconductor wafer. The method includes forming a feature of the host semiconductor wafer, wherein the feature includes a first conductive material and a surface having a planar region and non-planar regions. The method further includes forming a metal conductive liner over the non-planar regions. The method further includes applying a second conductive material metal layer over said the conductive liner. The method further includes recessing the second conductive material to be substantially planar with the planar region.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: November 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, John E. Sheets, II
  • Top via with next level line selective growth
    Patent number: 11171084
    Abstract: Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having a conductive thin metal layer on a top via that promotes the selective growth of the next level interconnect lines (the line above). In a non-limiting embodiment of the invention, a first conductive line is formed in a dielectric layer. A via is formed on the first conductive line and a seed layer is formed on the via and the dielectric layer. A surface of the seed layer is exposed and a second conductive line is deposited onto the exposed surface of the seed layer. In a non-limiting embodiment of the invention, the second conductive line is selectively grown from the seed layer.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: November 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent Anderson, Lawrence A. Clevenger, Christopher J. Penny, Nicholas Anthony Lanzillo, Kisik Choi, Robert Robison
  • Multiple patterning scheme integration with planarized cut patterning
    Patent number: 11171001
    Abstract: A semiconductor device includes at least one mandrel including a dielectric material, and at least one non-mandrel including a hard mask material having an etch property substantially similar to that of the dielectric material.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: November 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hsueh-Chung Chen, Yongan Xu, Lawrence A. Clevenger, Yann Mignot, Cornelius Brown Peethala