Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.

Abstract: A 3D identification filter (101) is provided, which has a passband partially overlapping with a wavelength range of 800 nm to 1800 nm and a blocking band containing a range of 380 nm to 750 nm, and comprises a substrate (102) and filter film layers (103, 104) coated on both surfaces of the substrate, wherein the filter film layer (103) on one of the surfaces is composed of high refractive index layers, medium refractive index layers, and low refractive index layers that are stacked, and the filter film layer (104) on the other surface is composed of at least two layers of materials that are stacked. The 3D identification filter (101) maintains a high bocking level and a narrow transition band while achieving a small wavelength shift at a large light incident angle.

Abstract: A method for estimating a state of charge of a battery includes obtaining a discharge voltage and discharge capacity curve of a battery under a preset discharge current, in responding to an order for estimating the state of charge of the battery; matching the discharge voltage and discharge capacity curve with a plurality of standard curves in a database, thereby obtaining an optimal matching curve with respect to the discharge voltage and discharge capacity curve; and calculating the state of charge of the battery according to the optimal matching curve, under a preset discharge stage. The present method can accurately calculate the state of charge of the battery with simple calculation manners.

Abstract: The present disclosure relates to a device and a method for measuring a thickness of an ultrathin film on a solid substrate. The thickness of the target ultrathin film is measured from the intensity of the fluorescence converted by the substrate and leaking and tunneling through the target ultrathin film at low detection angle. The fluorescence generated from the substrate has sufficient and stable high intensity, and therefore can provide fluorescence signal strong enough to make the measurement performed rapidly and precisely. The detection angle is small, and therefore the noise ratio is low, and efficiency of thickness measurement according to the method disclosed herein is high. The thickness measurement method can be applied into In-line product measurement without using standard sample, and therefore the thickness of the product can be measured rapidly and efficiently.

Abstract: A semiconductor package includes a semiconductor device including a first UBM structure, wherein the first UBM structure includes multiple first conductive strips, the first conductive strips extending in a first direction, multiple second conductive strips separated from and interleaved with the multiple first conductive strips, the second conductive strips extending in the first direction, wherein the multiple first conductive strips are offset in the first direction from the multiple second conductive strips by a first offset distance, and a substrate including a second UBM structure, the second UBM structure including multiple third conductive strips, each one of the multiple third conductive strips bonded to one of the multiple first conductive strips or one of the multiple second conductive strips.

Abstract: A dual-mode dielectric resonator using two dissimilar modes is described, the dissimilar modes supported by a ridge waveguide resonator and a ¼-wavelength (¼?) metalized cylindrical resonator within a single, metal-coated dielectric block. Each ridge waveguide resonator and cylindrical resonator form a dual-mode resonator pair. Coupling control posts set between the ridge waveguide resonator and cylindrical resonator can adjust their coupling. Multiple pairs of ridge waveguide/cylindrical resonators are fabricated in the same dielectric block to form a coupled resonator bandpass filter, including an 8-pole or 10-pole dielectric resonator filter, for 5G or other applications. Transmission zeros can be introduced by a metalized blind hole extending vertically between two ridge waveguide resonators or a microstrip extending between two dual-mode resonator pairs between which there exists no partial-width or full-width dielectric window.

Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.

Abstract: A package structure includes a die, a TIV, a first encapsulant, a RDL structure, a thermal dissipation structure and a second encapsulant. The die has a first surface and a second surface opposite to each other. The TIV is laterally aside the die. The first encapsulant encapsulates sidewalls of the die and sidewalls of the TIV. The RDL structure is disposed on the first surface of the die and on the first encapsulant, electrically connected to the die and the TIV. The thermal dissipation structure is disposed over the second surface of die and electrically connected to the die through the TIV and the RDL structure. The second encapsulant encapsulates sidewalls of the thermal dissipation structure.

Abstract: The present disclosure discloses a capacitive touch panel, including a substrate, wherein a first surface of the substrate includes a first region and a second region, and a second surface of the substrate includes a third region and a fourth region. A first group of drive lines is formed in the first region, a first group of sense lines is formed in the second region, a second group of the drive lines is formed in the third region, and a second group of the sense lines is formed in the fourth region. Each of the drive lines of the first group and the second group extends along a first direction from a periphery of the substrate to a middle of the substrate, with an end of said each drive line on the periphery of the substrate being connected to a drive chip.

Abstract: This disclosure relates to an apparatus and methods for applying X-ray reflectometry (XRR) in characterizing three dimensional nanostructures supported on a flat substrate with a miniscule sampling area and a thickness in nanometers. In particular, this disclosure is targeted for addressing the difficulties encountered when XRR is applied to samples with intricate nanostructures along all three directions, e.g. arrays of nanostructured poles or shafts. Convergent X-ray with long wavelength, greater than that from a copper anode of 0.154 nm and less than twice of the characteristic dimensions along the film thickness direction, is preferably used with appropriate collimations on both incident and detection arms to enable the XRR for measurements of samples with limited sample area and scattering volumes.

Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.

Abstract: A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.

Abstract: A dual-mode dielectric resonator using two dissimilar modes is described, the dissimilar modes supported by a ridge waveguide resonator and a ½-wavelength metalized cylindrical resonator within a single, metal-coated dielectric block. Each ridge waveguide resonator and cylindrical resonator form a resonator pair. Multiple pairs of ridge waveguide/cylindrical resonators are fabricated in the same dielectric block to form an 8-pole dielectric resonator filter for 5G or other applications. Transmission zeros can be positioned by the location of feeding probes along the cylindrical resonators.

Abstract: A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.

Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.

Abstract: A disc-type speed regulation magnetic coupler based on bevel gear drive is provided, consisting of a driving disc assembly and a driven disc assembly, wherein a speed regulation device is mounted on the driving disc assembly.

Abstract: The present invention relates to an in vitro immune synapse system and a method of in vitro evaluating immune response using the same. The in vitro immune synapse system includes antigen-presenting cells (APCs) and at least one cell type of several specific T cell subtypes isolated from peripheral blood mononuclear cells (PBMCs), all of which is from a same individual of pigs. When a test sample is co-cultured in the in vitro immune synapse system for a given period, it can be determined that the test sample is immunogenic, immunostimulatory or not according to the immunization-related changes of these cells, thereby potentially replacing some kinds of animal experimentation.

Abstract: Disclosed herein are agonistic anti-CD137 antibodies and methods of using such for eliciting CD137 signaling, thereby enhancing immune responses such as T cell functions. The antibodies disclosed within may be used to treat diseases, such as cancer and immune disorders.

Abstract: A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.