Patents by Inventor Li Wu

Li Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11855232
    Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20230408866
    Abstract: Disclosed are a backlight module and a curved display device. The backlight module includes a backplane and a backlight. The backplane includes a backplane body and two arc fixing components. The backplane body is provided with two opposite arc sides and each arc fixing component is correspondingly detachably installed at each arc side to restrict a curvature of the backplane body. A mounting groove is formed by the cooperative enclosure of two arc fixing components and an inner surface of the backplane body. The backlight is provided into the mounting groove.
    Type: Application
    Filed: December 9, 2022
    Publication date: December 21, 2023
    Applicants: BEIHAI HKC OPTOELECTRONICS TECHNOLOGY CO., LTD., HKC CORPORATION LIMITED
    Inventors: Li WU, HSU KANG LO, Haijiang YUAN
  • Publication number: 20230408756
    Abstract: A display apparatus and a display method are provided. The display apparatus includes a display panel, a display film assembly, a privacy film assembly, and a light source. The display film assembly includes a first light guide plate and an optical film. The optical privacy film assembly includes a second light guide plate and a privacy film. The privacy film is configured to adjust divergent lights exiting the second light guide plate into privacy lights at a preset angle. The light source is configured to emit incident lights to be selectively irradiated to the first light guide plate or the second light guide plate, so that the display apparatus is able to switch between a normal display mode and a privacy display mode.
    Type: Application
    Filed: December 28, 2022
    Publication date: December 21, 2023
    Applicant: HKC Corporation Limited
    Inventors: Li WU, Baohong KANG
  • Patent number: 11848218
    Abstract: Exemplary semiconductor chamber component cleaning systems may include a receptacle. The receptacle may include a bottom lid that may be an annulus. The annulus may be characterized by an inner annular wall and an outer annular wall. A plurality of recessed annular ledges may be defined between the inner annular wall and the outer annular wall. Each recessed annular ledge of the plurality of recessed annular ledges may be formed at a different radial position along the bottom lid. The cleaning systems may include a top lid removably coupled with the bottom lid about an exterior region of the top lid. The cleaning systems may include a tank defining a volume to receive the receptacle.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: December 19, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Katty Guyomard, Chidambara A. Ramalingam, Shawyon Jafari, Palash Joshi, Moin Ahmed Khan, Kirubanandan Naina Shanmugam, Subhaschandra Shreepad Salkod, Avishek Ghosh, David W. Groechel, Li Wu, Dorothea Buechel-Rimmel
  • Patent number: 11842993
    Abstract: A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: December 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Cheng Tseng, Yu-Chih Huang, Chih-Hsuan Tai, Ting-Ting Kuo, Chi-Hui Lai, Ban-Li Wu, Chiahung Liu, Hao-Yi Tsai
  • Publication number: 20230395490
    Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.
    Type: Application
    Filed: August 2, 2023
    Publication date: December 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Patent number: 11834647
    Abstract: The present invention relates to an in vitro immune synapse system and a method of in vitro evaluating immune response using the same. The in vitro immune synapse system includes antigen-presenting cells (APCs) and at least one cell type of several specific T cell subtypes isolated from peripheral blood mononuclear cells (PBMCs), all of which is from a same individual of pigs. When a test sample is co-cultured in the in vitro immune synapse system for a given period, it can be determined that the test sample is immunogenic, immunostimulatory or not according to the immunization-related changes of these cells, thereby potentially replacing some kinds of animal experimentation.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: December 5, 2023
    Assignee: National Pingtung University of Science and Technology
    Inventors: Hso-Chi Chaung, Wen-Bin Chung, Ann Ying-An Chen, Mei-Li Wu
  • Publication number: 20230380459
    Abstract: A preservation method of fresh tremella fuciformis suitable for cold-chain circulation includes pretreatment of fresh tremella fuciformis: selecting fresh tremella fuciformis with no mildew, no rot, no disease and insect pests, and water content?90% to enter subsequent cold-chain circulation; precooling: precooling the pretreated fresh tremella fuciformis put in a cold store at 1° C.-3° C., or performing vacuum precooling on the pretreated fresh tremella fuciformis; packaging, wherein a temperature of a packaging operation room of the fresh tremella fuciformis is less than or equal to 18° C., and time of the fresh tremella fuciformis from entering the packaging operation room to the completion of packaging does not exceed 1 h; storage: storing the packaged fresh tremella fuciformis immediately, controlling a storage temperature to 1° C.-3° C., and performing cold-chain transportation within 24 h; and cold-chain transportation: performing transportation by a refrigerated vehicle or by adding ice packs.
    Type: Application
    Filed: October 25, 2022
    Publication date: November 30, 2023
    Inventors: Pufu LAI, Junchen CHEN, Minjie WENG, Baosha TANG, Yibin LI, Li WU, Zheng XIAO, Yanrong YANG
  • Publication number: 20230352357
    Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.
    Type: Application
    Filed: July 12, 2023
    Publication date: November 2, 2023
    Inventors: Tsung-Hsien Chiang, Yu-Chih Huang, Ting-Ting Kuo, Chih-Hsuan Tai, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20230324814
    Abstract: An extreme ultra violet (EUV) lithography apparatus includes a light source that generates an EUV light beam, a scanner that receives the light from a junction with the light source and directs the light to a reticle stage, and a debris catcher disposed on a EUV beam path between the light source and the scanner. The debris catcher includes a network membrane including a plurality of nano-fibers.
    Type: Application
    Filed: April 11, 2022
    Publication date: October 12, 2023
    Inventors: I-Hsiung HUANG, Yung-Cheng CHEN, Tung-Li WU
  • Patent number: 11757003
    Abstract: A bonding wafer structure includes a support substrate, a bonding layer, and a silicon carbide (SiC) layer. The bonding layer is formed on a surface of the support substrate, and the SiC layer is bonded onto the bonding layer, in which a carbon surface of the SiC layer is in direct contact with the bonding layer. The SiC layer has a basal plane dislocation (BPD) of 1,000 ea/cm2 to 20,000 ea/cm2, a total thickness variation (TTV) greater than that of the support substrate, and a diameter equal to or less than that of the support substrate. The bonding wafer structure has a TTV of less than 10 ?m, a bow of less than 30 ?m, and a warp of less than 60 ?m.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: September 12, 2023
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Ying-Ru Shih, Wei Li Wu, Hung-Chang Lo
  • Patent number: 11742254
    Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Hsien Chiang, Yu-Chih Huang, Ting-Ting Kuo, Chih-Hsuan Tai, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20230251258
    Abstract: Methods and systems for improved labeling and/or de-labeling a molecule or cell in the context of scientific experimentation, industrial applications, and clinical investigation, including the means to repeat the process of labeling and de-labeling in an efficient manner.
    Type: Application
    Filed: April 20, 2023
    Publication date: August 10, 2023
    Applicant: University of Washington
    Inventors: Daniel T. Chiu, Chun-Ting Kuo, Li Wu
  • Publication number: 20230253384
    Abstract: A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Inventors: Yu-Chih Huang, Chi-Hui Lai, Ban-Li Wu, Ying-Cheng Tseng, Ting-Ting Kuo, Chih-Hsuan Tai, Hao-Yi Tsai, Chuei-Tang Wang, Chung-Shi Liu, Chen-Hua Yu, Chiahung Liu
  • Publication number: 20230223357
    Abstract: A method of manufacturing a semiconductor package includes depositing a first dielectric layer over a carrier substrate. A first metallization pattern is formed over the first dielectric layer. The first metallization pattern has a first opening exposing the first dielectric layer. A second dielectric layer is deposited over the first metallization pattern, forming a dielectric slot through the first metallization pattern by filling the first opening. A second metallization pattern and a third dielectric layer are formed over the second dielectric layer. A through via is formed over the third dielectric layer, so that the dielectric slot is laterally under the through via.
    Type: Application
    Filed: May 24, 2022
    Publication date: July 13, 2023
    Inventors: Yi-Che Chiang, Chien-Hsun Chen, Tuan-Yu Hung, Hsin-Yu Pan, Wei-Kang Hsieh, Tsung-Hsien Chiang, Chao-Hsien Huang, Tzu-Sung Huang, Ming Hung Tseng, Wei-Chih Chen, Ban-Li Wu, Hao-Yi Tsai, Yu-Hsiang Hu, Chung-Shi Liu
  • Patent number: 11698493
    Abstract: A single-ended output circulator includes a three-core optical fiber head having first, second, and third optical fiber cores; a walk-off crystal having a first surface facing towards the second end of the three-core optical fiber head tube and a second surface facing away from the second end of the three-core optical fiber head tube; a plurality of half-wave plates each having a first surface coupled to the second surface of the walk-off crystal and a second surface facing away from the second surface of the walk-off crystal; a collimating lens having a first end and a second end; a reflection mirror configured to reflect light beams from the collimating lens; an optical prism between the collimating lens and the reflection mirror and configured to transmit a light beam along a propagation direction according to a polarization direction of the light beam; and a polarization rotator.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: July 11, 2023
    Assignee: II-VI DELAWARE, INC.
    Inventors: Li Wu, Yunbing Xu, Weimin Chen, Yuping Wu, Danping Wei, Peng Xiao, Yang Li, Hongming Cai
  • Patent number: 11690146
    Abstract: A microwave separated field reconstructed device includes: a microwave field reconstructed cavity, a first short circuit plane, a third waveguide flange and coupling windows, wherein connection ports are provided on four ends of the microwave field reconstructed cavity; the microwave field reconstructed cavity is provided with a first waveguide flange, and a second waveguide flange is provided one end of the microwave field reconstructed cavity perpendicular to the first waveguide flange; the first short circuit plane is connected to one end of the first waveguide flange away from the microwave field reconstructed cavity; a second short circuit plane is connected to one end of the second waveguide flange away from the microwave field reconstructed cavity. The input ports are distributed at two ends of the microwave field reconstructed cavity to introduce electric and magnetic fields.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: June 27, 2023
    Assignee: Sichuan University
    Inventors: Kama Huang, Yi Zhang, Yang Yang, Huacheng Zhu, Li Wu, Bing Zhang
  • Patent number: 11668713
    Abstract: Methods and systems for improved labeling and/or de-labeling a molecule or cell in the context of scientific experimentation, industrial applications, and clinical investigation, including the means to repeat the process of labeling and de-labeling in an efficient manner.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: June 6, 2023
    Assignee: UNIVERSITY OF WASHINGTON
    Inventors: Daniel T. Chiu, Chun-Ting Kuo, Li Wu
  • Patent number: 11631658
    Abstract: A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: April 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Chih Huang, Chi-Hui Lai, Ban-Li Wu, Ying-Cheng Tseng, Ting-Ting Kuo, Chih-Hsuan Tai, Hao-Yi Tsai, Chuei-Tang Wang, Chung-Shi Liu, Chen-Hua Yu, Chiahung Liu
  • Patent number: 11629814
    Abstract: An angle-adjustable supporting mechanism that includes a knob-type locking mechanism and a rotatable holder is provided. The knob-type locking mechanism has a base, a knob, and a latch member. The base has a receiving space and a supporting portion. The knob is rotatably received in the receiving space. The latch member is movably received in the supporting portion in a linear direction. The latch member has a bolt, a first stressed part, and a second stressed part. The bolt is disposed at one side of the first stressed part. The first stressed part is disposed between the bolt and the second stressed part. When the knob is rotated in different directions, the bolt of the latch member is drove to lock or release.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: April 18, 2023
    Assignee: WISTRON NEWEB CORPORATION
    Inventor: Jhan-Li Wu