Abstract: An endoscope device includes an operation processor and a detection module. The detection module is electrically connected with the operation processor. The detection module includes a tube, an optical transmission component, an optical detector, a signal transmission component, a first holder and a second holder. The optical transmission component has a first part and a second part bent to each other. The optical detector is located above the first part. The signal transmission component is coupled with the optical detector, and is parallel to the second part, and bent from a detection surface of the optical detector. The first holder includes a first accommodating structure adapted to accommodate the optical detector. The second holder includes a second accommodating structure adapted to accommodate the first part, and the optical transmission component and the optical detector are assembled between the first holder and the second holder to install inside the tube.

Abstract: Some implementations described herein include techniques and apparatus for forming a semiconductor device including a semiconductor resistor structure. The semiconductor resistor structure (e.g., a low-impedance thin-film resistor structure) may include a resistive layer having an approximately rectangular shape (e.g., a width-to-length ratio that is less than approximately one). The semiconductor resistor structure includes contact structures connected to the resistive layer, a conductive bus structure having an approximately rectangular shape that connects to the contact structures, and an electrical terminal (e.g., a routing pin) centrally located at or near an edge of the conductive bus structure.

Abstract: A method for forming a semiconductor memory device is disclosed. A substrate is provided. A pair of floating gates are formed on the substrate. A recessed region is formed in the substrate between the floating gates, wherein an upper surface of the recessed region has a concave profile lower than a surface of the substrate and with a radius between 40 nm and 60 nm in a cross-sectional view perpendicular to the floating gates. A source line doped region is formed in the recessed region. An erase gate is formed between the floating gates and on the recessed region, and a word line is formed on the substrate and adjacent to a side of each of the floating gates opposite to the erase gate. A bit line doped region is formed in the substrate and adjacent to the word line.

Abstract: A semiconductor memory device includes a substrate, an active region defined in the substrate by a trench isolation structure, a pair of floating gates on the substrate and at two sides of a fish-bone shaped recessed region of the active region, a source line doped region in the fish-bone shaped recessed region of the active region, wherein a bottom surface of the source line doped region extends above a bottom surface of the trench isolation structure, an erase gate disposed between the floating gates and on the source line doped region, a word line disposed on the substrate and adjacent to a side of each of the floating gates opposite to the erase gate, and a bit line doped region in the substrate and adjacent to the word line.

Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic structure and a wall structure surrounding the electronic structure are disposed on a carrier structure, a heat conducting layer is formed on the electronic structure, and the wall structure and the heat conducting layer are covered by a heat dissipation element. Therefore, a thermal stress can be effectively dispersed by the arrangement of the wall structure, such that a warpage of the electronic structure and a heat dissipation body can be effectively controlled.

Abstract: A method for forming a semiconductor memory device is disclosed. A substrate is provided. A source diffusion region is formed in the substrate. Two floating gates are on opposite sides of the source diffusion region. A first dielectric cap layer is formed directly on each of the floating gates. An erase gate is formed on the source diffusion region. The erase gate partially overlaps an upper inner corner of each of the floating gates. A second dielectric cap layer is formed on the erase gate and the first dielectric cap layer. A select gate is formed on a sidewall of the first dielectric cap layer in a self-aligned manner. A drain diffusion region is formed in the substrate and adjacent to the select gate.

Abstract: A semiconductor memory device includes a substrate, a pair of floating gates disposed on the substrate, a source line doped region in the substrate between the floating gates, an erase gate disposed between the floating gates and on the source line doped region, a word line disposed on the substrate and adjacent to a side of each of the floating gates opposite to the erase gate, and a bit line doped region in the substrate and adjacent to the word line. An upper surface of the source line doped region has a concave profile lower than a surface of the substrate and with a radius between 40 nm and 60 nm in a cross-sectional view perpendicular to the floating gates.

Abstract: The present invention discloses a method for monitoring an exercise. The method comprises: building up an energy metabolism system having an energy metabolism feature, wherein the energy metabolism feature comprises a first feature factor, wherein the first feature factor is associated with a first biological system being one of a plurality of biological systems of a human body and not associated with the complete human body; building up a mathematical model describing that an energy expenditure depends on at least one exercise-associated parameter based on the energy metabolism feature for the energy metabolism system; estimating the energy expenditure based on the at least one exercise-associated parameter measured in the exercise by the mathematical model of the energy metabolism system; and monitoring the exercise based on the energy expenditure.

Abstract: An atomic layer deposition apparatus for coating on fine powders is disclosed, which includes a vacuum chamber, a shaft sealing device, and a driving unit. The shaft sealing device includes an outer tube and an inner tube arranged in an accommodating space of the outer tube. The driving unit drives the vacuum chamber to rotate through the outer tube to agitate the fine powders in a reaction space of the vacuum chamber. An air extraction line and an air intake line are arranged in a connection space of the inner tube. The air extraction line is used to extract gas from the reaction space. The air intake line is used to transport non-reactive gas to the reaction space to blow the fine powders around in the reaction space and precursor gas to the reaction space to form thin films with uniform thickness on the surface of the fine powders.

Abstract: A distance determination method has: detecting a first received signal strength indicator (RSSI) of a first electronic device by a second electronic device; detecting a second RSSI of the second electronic device by the first electronic device; obtaining the first RSSI from the second electronic device by the first electronic device; and calculating a motion direction and a distance of the second electronic device relative to the first electronic device according to the first RSSI and the second RSSI by the first electronic device.

Abstract: A method of generating an IC layout diagram includes receiving an IC layout diagram including a gate region and a gate via, the gate via being positioned at a location within an active region and along a width of the gate region extending across the active region, receiving a first gate resistance value of the gate region, retrieving a second gate resistance value from a resistance value reference based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.

Abstract: An endoscopic device is provided and includes an insertion tube, an imaging assembly, a light guiding component and a light emitting component. The imaging assembly includes a lens set and an image sensor. The lens set is located adjacent to a distal end of the insertion tube. The image sensor is located inside the insertion tube and engaged with the lens set. The light guiding component is located adjacent to the distal end of the insertion tube and beside the lens set. The light guiding component includes an outer end adjacent to the distal end of the insertion tube and an inner end opposite to the outer end. A length of the light guiding component is greater than a length of the imaging assembly. The light emitting component is located inside the insertion tube and adjacent to the inner end of the light guiding component.

Abstract: A detection device includes a frame, a transport mechanism, detection mechanisms, and a grasping mechanism. The transport mechanism includes a feeding line, a first flow line, and a second flow line arranged in parallel on the frame. The detection mechanisms are arranged on the frame and located on two sides of the transport mechanism. The grasping mechanism is arranged on the frame and used to transport workpieces on the feeding line to the detection mechanisms, transport qualified workpieces to the first flow line, and transport unqualified workpieces to the second flow line.

Abstract: Disclosed is a power storage device and method for discharging the same, which configures the power storage device to perform an electric power output under a discharging limit upon coupling with a load device and before any authentication is conducted. The discharging limit for the electric power output will be lifted only when an authentication result between the power storage device and the load device indicates a successful authentication.

Abstract: A semiconductor memory device includes a semiconductor substrate, a select gate on the semiconductor substrate, a control gate disposed adjacent to the select gate and having a first sidewall and a second sidewall, and a charge storage layer between the control gate and the semiconductor substrate. The control gate includes a third sidewall close to the second sidewall of the select gate, a fourth sidewall opposite to the third sidewall, and a non-planar top surface between the third sidewall and the fourth sidewall. The non-planar top surface includes a first surface region that descends from the third sidewall to the fourth sidewall. The charge storage layer extends to the second sidewall of the select gate.

Abstract: A method of manufacturing an electronic package is provided, in which an electronic element is disposed on a carrier structure; a heat dissipation body of a heat dissipation structure is disposed on the electronic element via a heat dissipation material; the heat dissipation material is cured; supporting legs of the heat dissipation structure are fixed on the carrier structure via a bonding layer; and the bonding layer is cured. Therefore, the heat dissipation structure can be effectively fixed to the heat dissipation material and the bonding layer by completing the arrangements of the heat dissipation material and the bonding layer in stages.

Abstract: A memory device includes a semiconductor substrate, isolation structures, an erase gate, and floating gates. The isolation structures are disposed in the semiconductor substrate. Active regions separated from one another are defined in the semiconductor substrate by the isolation structures, and each of the active regions is elongated in a first direction. The erase gate is disposed on the semiconductor substrate and elongated in a second direction. The erase gate is disposed on the active regions and the isolation structures, and the erase gate is partly disposed in a recess within each of the isolation structures. The floating gates are disposed on the semiconductor substrate. The floating gates are arranged in the second direction and separated from one another, and each of the floating gates is partly disposed under the erase gate in a vertical direction.

Abstract: A method of generating an IC layout diagram includes receiving a first gate resistance value of a gate region in an IC layout diagram, the first gate resistance value corresponding to a location of a gate via positioned within an active region and along a width of the gate region extending across the active region, determining a second gate resistance value based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell for FinFET includes a fin, a control gate and a selective metal gate. The fin is on a top surface of a substrate, wherein the fin has two sidewalls and a top surface, and the fin includes a memory region and a logic region. The control gate is disposed over the fin of the memory region and covers the two sidewalls and the top surface of the fin, wherein the control gate includes a charge trapping layer and a control electrode, wherein the charge trapping layer is sandwiched by the fin and the control electrode. The selective metal gate is disposed over the fin adjacent to the control gate and covers the two sidewalls and the top surface of the fin. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell for FinFET includes a fin, a control gate and a selective metal gate. The fin is on a top surface of a substrate, wherein the fin has two sidewalls and a top surface, and the fin includes a memory region and a logic region. The control gate is disposed over the fin of the memory region and covers the two sidewalls and the top surface of the fin, wherein the control gate includes a charge trapping layer and a control electrode, wherein the charge trapping layer is sandwiched by the fin and the control electrode. The selective metal gate is disposed over the fin adjacent to the control gate and covers the two sidewalls and the top surface of the fin. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.