Patents by Inventor LIANG YI

LIANG YI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230402517
    Abstract: A semiconductor memory device includes a substrate, a pair of floating gates disposed on the substrate, a source line doped region in the substrate between the floating gates, an erase gate disposed between the floating gates and on the source line doped region, a word line disposed on the substrate and adjacent to a side of each of the floating gates opposite to the erase gate, and a bit line doped region in the substrate and adjacent to the word line. An upper surface of the source line doped region has a concave profile lower than a surface of the substrate and with a radius between 40 nm and 60 nm in a cross-sectional view perpendicular to the floating gates.
    Type: Application
    Filed: June 9, 2022
    Publication date: December 14, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Liang Yi, CHI REN
  • Publication number: 20230380154
    Abstract: A structure of memory device includes an active region in a substrate, a dielectric layer on the active region, and a floating gate disposed on the dielectric layer. The active region extends along a first direction in a top-view. The floating gate includes a first protruding structure extending along the first direction from a sidewall of the floating gate protruding from a top surface of the substrate. The whole of the first protruding structure is located in the active region.
    Type: Application
    Filed: August 4, 2023
    Publication date: November 23, 2023
    Applicant: United Microelectronics Corp.
    Inventors: Liang Yi, Zhiguo Li, Chi Ren, Qiuji Zhao, Boon Keat Toh
  • Publication number: 20230370024
    Abstract: Embodiments of this application provide a multiband power amplifier circuit and a radio frequency transceiver, to increase a VBW while ensuring linear correction and reducing a circuit loss. The multiband power amplifier circuit includes a first power transistor, a second power transistor, a first matching circuit, a second matching circuit, a third matching circuit, and a combiner. The first power transistor is coupled to a first input end of the combiner via the first matching circuit. The second power transistor is coupled to a second input end of the combiner via the second matching circuit. A first end of the third matching circuit is coupled to an output end of the first power transistor, and a second end of the third matching circuit is coupled to an output end of the second power transistor.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 16, 2023
    Inventors: Hailei Suo, Liang Yi, Yijun Sun, Jie Sun
  • Publication number: 20230299160
    Abstract: A method for forming a semiconductor memory device is disclosed. A substrate is provided. A source diffusion region is formed in the substrate. Two floating gates are on opposite sides of the source diffusion region. A first dielectric cap layer is formed directly on each of the floating gates. An erase gate is formed on the source diffusion region. The erase gate partially overlaps an upper inner corner of each of the floating gates. A second dielectric cap layer is formed on the erase gate and the first dielectric cap layer. A select gate is formed on a sidewall of the first dielectric cap layer in a self-aligned manner. A drain diffusion region is formed in the substrate and adjacent to the select gate.
    Type: Application
    Filed: May 21, 2023
    Publication date: September 21, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Liang Yi, ZHIGUO LI, Xiaojuan Gao, CHI REN
  • Patent number: 11765893
    Abstract: A structure of memory device includes trench isolation lines in a substrate, extending along a first direction. An active region in the substrate is between adjacent two of the trench isolation lines. A dielectric layer is disposed on the active region of the substrate. A floating gate corresponding to a memory cell is disposed on the dielectric layer between adjacent two of the trench isolation lines. The floating gate has a first protruding structure at a sidewall extending along the first direction. A first insulating layer crosses over the floating gate and the trench isolation lines. A control gate line is disposed on the first insulating layer over the floating gate, extending along a second direction intersecting with the first direction. The control gate line has a second protruding structure correspondingly stacked over the first protruding structure of the floating gate, and crosses over the trench isolation lines.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: September 19, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Liang Yi, Zhiguo Li, Chi Ren, Qiuji Zhao, Boon Keat Toh
  • Patent number: 11744449
    Abstract: An endoscopy system including an insertion tube segment, a handle segment, at least one heat source, a heat pipe and a heat-conductive material is provided. The insertion tube segment has first and second end portions opposite to each other and is inserted in the handle segment. An inside of the insertion tube segment and an inside of the handle segment commonly have a connecting space. The at least one heat source is disposed in the first end portion. The heat pipe is disposed in the connecting space and at least extends from a portion of the connecting space of the insertion tube segment to a portion of the connecting space of the handle segment. The heat-conductive material is disposed between the at least one heat source and the first end portion, and the heat-conductive material is thermally coupled to the at least one heat source and the heat pipe, respectively.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: September 5, 2023
    Assignee: ALTEK BIOTECHNOLOGY CORPORATION
    Inventors: Hsi-Hsin Loo, Chun-Wei Liu, Liang-Yi Li
  • Publication number: 20230268390
    Abstract: A semiconductor device structure includes nanostructures formed over a substrate. The structure also includes a fin isolation structure formed beside the nanostructures. The structure also includes a work function layer surrounding the nanostructures and covering a sidewall of the fin isolation structure. The structure also includes a gate electrode layer covering the work function layer. The gate electrode layer has an extending portion surrounded by the work function layer.
    Type: Application
    Filed: February 23, 2022
    Publication date: August 24, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Fai CHENG, Liang-Yi CHEN, Chi-An WANG, Kuan-Chung CHEN, Chih-Wei LEE
  • Patent number: 11697392
    Abstract: The present disclosure relates to security mechanisms for electric motors and associated systems. For example, the present technology includes a powertrain assembly having (1) a motor having multiple sets of coils; (2) a drive circuitry electrically coupled to the multiple sets of coils; and (3) a security unit electrically coupled to the drive circuitry and the multiple sets of coils. The security unit is configured to short-circuit at least one set of the multiple sets of coils responsive to a signal from a controller. The signal indicates that the motor is, or has been, turned off.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: July 11, 2023
    Assignee: Gogoro Inc.
    Inventors: Shih-Yuan Lin, Yu-Se Liu, Liang-Yi Hsu
  • Patent number: 11699730
    Abstract: A semiconductor memory device includes a substrate; a source diffusion region in the substrate; a pair of floating gates disposed on opposite of the source diffusion region; a first dielectric cap layer disposed directly on each of the floating gates; an erase gate disposed on the source diffusion region and partially overlapping an upper inner corner of each of the floating gates; a second dielectric cap layer disposed on the erase gate and the first dielectric cap layer; a select gate disposed on a sidewall of the first dielectric cap layer; and a drain diffusion region disposed in the substrate and adjacent to the select gate.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: July 11, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Liang Yi, Zhiguo Li, Xiaojuan Gao, Chi Ren
  • Publication number: 20230185294
    Abstract: An energy storage device includes a sensor, a communication circuit and a processor. The sensor is configured to detect an abnormal event occurred in the energy storage device. The communication circuit is configured to connect to a local area network. The local area network includes a plurality of nodes formed by the energy storage device and other energy storage devices. The processor is configured to generate, according to the abnormal event detected by the sensor, historical usage data recording the abnormal event. In response to a trigger event, the processor is further configured to: update the historical usage data; and control the communication circuit to transmit at least part of the updated historical usage data to at least one energy storage device adjacent to the energy storage device in the local area network.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 15, 2023
    Inventors: Liang-Yi Hsu, I-Sheng Chen, Yong-Sheng Chen, Wei-Tsung Huang
  • Patent number: 11650705
    Abstract: A touch panel is provided in the present disclosure, including: a substrate, a conductive trace structure, and a light-shielding structure. The substrate includes a visible area and a peripheral area, and the visible area is surrounded by the peripheral area. A conductive trace structure is disposed on the visible area. The light-shielding structure includes a first material layer and a second material layer, in which the optical density of the light-shielding structure is lower than 4, the first material layer is disposed on the peripheral area, and the second material layer is disposed on the first material layer. A method of manufacturing a touch panel is provided in some embodiments of the present disclosure for the effects of saving cost and improving wire drift.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: May 16, 2023
    Assignee: TPK Advanced Solutions Inc.
    Inventors: Wei You Hsu, Wei-Chen Huang, Liang-Yi Chang, Han-Wei Chen, Ho-Chien Wu
  • Patent number: 11616333
    Abstract: An endoscope device and a cable assembly thereof are provided. The cable assembly includes a first substrate, a second substrate, and a wire. The first substrate includes a first body and a first solder pad disposed on the first body. The second substrate is correspondingly disposed on the first substrate and includes a second body, a second solder pad disposed on the second body and corresponding to the first solder pad, and an accommodating portion corresponding to the second solder pad. The wire includes a soldering portion disposed in the accommodating portion. The first solder pad and the second solder pad are coupled to each other by at least one of a first solder and a second solder, and the soldering portion and the second solder pad are coupled to each other by the first solder.
    Type: Grant
    Filed: September 2, 2019
    Date of Patent: March 28, 2023
    Assignee: ALTEK BIOTECHNOLOGY CORPORATION
    Inventors: Hsi-Hsin Loo, Parn-Far Chen, Liang-Yi Li, Chao-Yu Chou
  • Publication number: 20230045722
    Abstract: A semiconductor memory device includes a semiconductor substrate, a select gate on the semiconductor substrate, a control gate disposed adjacent to the select gate and having a first sidewall and a second sidewall, and a charge storage layer between the control gate and the semiconductor substrate. The control gate includes a third sidewall close to the second sidewall of the select gate, a fourth sidewall opposite to the third sidewall, and a non-planar top surface between the third sidewall and the fourth sidewall. The non-planar top surface includes a first surface region that descends from the third sidewall to the fourth sidewall. The charge storage layer extends to the second sidewall of the select gate.
    Type: Application
    Filed: September 7, 2021
    Publication date: February 9, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Liang Yi, Zhiguo Li, Chi Ren, Xiaojuan Gao, Boon Keat Toh
  • Publication number: 20230029468
    Abstract: A semiconductor memory device includes a substrate; a source diffusion region in the substrate; a pair of floating gates disposed on opposite of the source diffusion region; a first dielectric cap layer disposed directly on each of the floating gates; an erase gate disposed on the source diffusion region and partially overlapping an upper inner corner of each of the floating gates; a second dielectric cap layer disposed on the erase gate and the first dielectric cap layer; a select gate disposed on a sidewall of the first dielectric cap layer; and a drain diffusion region disposed in the substrate and adjacent to the select gate.
    Type: Application
    Filed: October 25, 2021
    Publication date: February 2, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Liang Yi, ZHIGUO LI, Xiaojuan Gao, CHI REN
  • Publication number: 20230035590
    Abstract: A light-guiding structure according to the invention is used in an endoscope for guiding light along a lengthwise direction and includes a first portion and a second portion. The first portion extends in a single cross section along the lengthwise direction. The second portion extends in a varying cross section along the lengthwise direction and is connected to an end of the first portion in the lengthwise direction. An endoscope tip includes a circuit board, an image-capturing component, a light-emitting component, and the light-guiding structure. The light-guiding structure can fit the contours of the circuit board and the image-capturing component to increase space usage for obtaining more cross-sectional area. For the production of the light-guiding structure, the second portion is formed by shaping a portion directly extending form the end of the first portion or by an additional material directly bonded to the end of the first portion by molding.
    Type: Application
    Filed: July 29, 2021
    Publication date: February 2, 2023
    Applicant: ALTEK BIOTECHNOLOGY CORPORATION
    Inventors: Hsi-Hsin Loo, Liang-Yi Li
  • Patent number: 11535938
    Abstract: A shower head assembly of an atomic layer deposition device has a first trapezoidal column component, a second trapezoidal column component and a column component, wherein a first bottom edge of the first trapezoidal column component is connected to a second top edge of the second trapezoidal column component, and a second bottom edge of the second trapezoidal column component is connected to a top edge of the column component. The first trapezoidal column component has a first bottom dimension distance, the second trapezoidal column component has a second vertical distance, and the column component has a column vertical distance, wherein a ratio of the column vertical distance to the second vertical distance is greater than or equal to 1.2, and a total distance of the second vertical distance and the column vertical distance is less than the first bottom dimension distance.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: December 27, 2022
    Assignee: SKY TECH INC.
    Inventors: Jing-Cheng Lin, Ching-Liang Yi, Yun-Chi Hsu
  • Publication number: 20220406109
    Abstract: A distance determination method has: detecting a first received signal strength indicator (RSSI) of a first electronic device by a second electronic device; detecting a second RSSI of the second electronic device by the first electronic device; obtaining the first RSSI from the second electronic device by the first electronic device; and calculating a motion direction and a distance of the second electronic device relative to the first electronic device according to the first RSSI and the second RSSI by the first electronic device.
    Type: Application
    Filed: June 2, 2022
    Publication date: December 22, 2022
    Inventors: Liang-Yi Hsu, I-Sheng Chen, Yong-Sheng Chen, Wei-Tsung Huang
  • Patent number: 11494013
    Abstract: A touch panel includes a cover plate, a first adhesive component, and a second adhesive component. The first adhesive component which is adhered underneath the cover plate, includes a plurality of first pattered sensing lines. The second adhesive component which is adhered underneath the first adhesive component, includes a plurality of second pattered sensing lines. The first pattered sensing lines and second pattered sensing lines are electrically insulated from each other.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: November 8, 2022
    Assignee: TPK Film Solutions (Xiamen) Inc.
    Inventors: Liang-Yi Chang, Chien-Hung Kuan, Renqing Peng, Jiachun Li
  • Patent number: D973040
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: December 20, 2022
    Inventors: Liang-Yi Liu, Hung-Wen Hsu, Che-Cheng Chang, Jian-Lun Chen
  • Patent number: D981378
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: March 21, 2023
    Inventors: Liang-Yi Liu, Ming-Huei Lai, Che-Cheng Chang, Jian-Lun Chen