Abstract: An endoscope device includes an insertion portion. The insertion portion includes a distal end. The distal end includes a lens holder, a lens disposed in the lens holder, an image sensor corresponding to the lens and a flexible circuit board electrically connected to the image sensor and a circuit board holder. The flexible circuit board is jointly clamped by the circuit board holder and the lens holder.

Abstract: A source/drain (S/D) structure includes a SiGe structure epitaxially grown and having sloped facets on a recessed fin structure disposed adjacent to a channel portion of a finFET, a first Ge structure having a rounded surface epitaxially grown on the SiGe structure, and a capping layer formed over the rounded surface of the Ge structure. The capping layer may be formed of Si. Such S/D structures provide both a larger physical size for lower contact resistance, and greater volume and concentration of Ge for higher compressive strain applied to the channel portion of the finFET.

Abstract: An endoscopy system including an insertion tube segment, a handle segment, at least one heat source, a heat pipe and a heat-conductive material is provided. The insertion tube segment has first and second end portions opposite to each other and is inserted in the handle segment. An inside of the insertion tube segment and an inside of the handle segment commonly have a connecting space. The at least one heat source is disposed in the first end portion. The heat pipe is disposed in the connecting space and at least extends from a portion of the connecting space of the insertion tube segment to a portion of the connecting space of the handle segment. The heat-conductive material is disposed between the at least one heat source and the first end portion, and the heat-conductive material is thermally coupled to the at least one heat source and the heat pipe, respectively.

Abstract: A stem includes a stem body, a column and a locking device. The stem body is provided with a perforation. The column is disposed at one end of the stem body and provided with a first aperture, the perforation is communicated with the first aperture. The locking device is disposed in the perforation and includes a clamping part, two sliding blocks and a first fixing member, the clamping part is located between the sliding blocks, and the first fixing member penetrates the clamping part and the sliding blocks. When the first fixing member moves toward inside of the perforation, the first fixing member drives the sliding blocks to approach each other and squeeze the clamping part, such that the clamping part moves in a direction toward the first aperture. According to this, the assembly and disassembly procedures of the present invention are quite simple and easy to operate.

Abstract: A structure of memory device includes trench isolation lines in a substrate, extending along a first direction. An active region in the substrate is between adjacent two of the trench isolation lines. A dielectric layer is disposed on the active region of the substrate. A floating gate corresponding to a memory cell is disposed on the dielectric layer between adjacent two of the trench isolation lines. The floating gate has a first protruding structure at a sidewall extending along the first direction. A first insulating layer crosses over the floating gate and the trench isolation lines. A control gate line is disposed on the first insulating layer over the floating gate, extending along a second direction intersecting with the first direction. The control gate line has a second protruding structure correspondingly stacked over the first protruding structure of the floating gate, and crosses over the trench isolation lines.

Abstract: A structure of nonvolatile memory device includes a substrate, having a logic device region and a memory cell region. A first gate structure for a low-voltage transistor is disposed over the substrate in the logic device region, wherein the first gate structure comprises a single-layer polysilicon. A second gate structure for a memory cell is disposed over the substrate in the memory cell region. The second gate structure includes a gate insulating layer on the substrate. A floating gate layer is disposed on the gate insulating layer, wherein the floating gate layer comprises a first polysilicon layer and a second polysilicon layer as a stacked structure. A memory dielectric layer is disposed on the floating gate layer. A control gate layer is disposed on the memory dielectric layer, wherein the control gate layer and the single-layer polysilicon are originated from a preliminary polysilicon layer in same.

Abstract: Multi-layer photoresists, methods of forming the same, and methods of patterning a target layer using the same are disclosed. In an embodiment, a method includes depositing a reflective film stack over a target layer, the reflective film stack including alternating layers of a first material and a second material, the first material having a higher refractive index than the second material; depositing a photosensitive layer over the reflective film stack; patterning the photosensitive layer to form a first opening exposing the reflective film stack, patterning the photosensitive layer including exposing the photosensitive layer to a patterned energy source, the reflective film stack reflecting at least a portion of the patterned energy source to a backside of the photosensitive layer; patterning the reflective film stack through the first opening to form a second opening exposing the target layer; and patterning the target layer through the second opening.

Abstract: A structure of memory device includes trench isolation lines in a substrate, extending along a first direction. An active region in the substrate is between adjacent two of the trench isolation lines. A dielectric layer is disposed on the active region of the substrate. A floating gate corresponding to a memory cell is disposed on the dielectric layer between adjacent two of the trench isolation lines. The floating gate has a first protruding structure at a sidewall extending along the first direction. A first insulating layer crosses over the floating gate and the trench isolation lines. A control gate line is disposed on the first insulating layer over the floating gate, extending along a second direction intersecting with the first direction. The control gate line has a second protruding structure correspondingly stacked over the first protruding structure of the floating gate.

Abstract: A game machine with a controllable an opening angle is characterized in that: including: a main body, having two lateral plates, an accommodation space and a mounting rod, wherein a front end of the accommodation space has a front opening; a movable gate, disposed at the front opening, wherein a rear end of the movable gate has a pivotal part pivoted to top end of the main body; and a movable mounting rack, having one end thereof disposed at a rear end of the movable gate and having two lateral mounting plates and at least one connection rod between the two lateral mounting plates, the lateral mounting plates are disposed at two sides of the movable mounting rack, the lateral mounting plates correspondingly have at least two mounting slots allowing the mounting rod to be mounted; a retractable rod is disposed between the moveable gate and the main body.

Abstract: The present disclosure relates to a hub apparatus and associated charging systems. In some embodiments, the hub apparatus includes (1) a housing assembly defining an internal space; (2) a shaft positioned to extend through the housing assembly; (3) a stator assembly fixedly coupled to the shaft; (4) a side cover fixedly coupled to the shaft and rotatably coupled to the housing assembly, the side cover having a base portion and a mating portion extending from the base portion; and (5) a pair of first connectors positioned through the mating portion. Each of the first connectors comprising a terminal end and a contact portion. The terminal end is electrically coupled to a battery assembly via a wire bundle fixedly coupled to the side cover. The contact portion is configured to electrically couple to an external power source so as to charge the battery assembly through a wired connection.

Abstract: A method of forming touch panels includes providing a substrate with a visible area and a periphery area, forming a metal layer, forming a metal nanowire layer with a first portion in the visible area and a second portion in the periphery area, and performing a patterning process. Forming the metal layer includes substrate pre-treatment, adjusting a characteristic of the substrate surface, forming a catalytic center on the substrate surface, adjusting an activity of the catalytic center, and performing electroless plating on the substrate surface to form the metal layer. The patterning process includes forming a plurality of periphery lead wires from the metal layer while forming a plurality of etching layer from the metal nanowire layer using an etchant that etches the metal layer and the metal nanowire layer.

Abstract: A method of generating a netlist of an IC device includes receiving gate region information of the IC device. The gate region information includes a width of the gate region, the width extending at least from a first edge of an active region to a second edge of the active region, a location of a gate via positioned within the active region and along the width, and a first gate resistance value corresponding to the gate region. The method includes determining a second gate resistance value based on the location and the width, and modifying the netlist based on the second gate resistance value.

Abstract: A structure of nonvolatile memory device includes a substrate, having a logic device region and a memory cell region. A first gate structure for a low-voltage transistor is disposed over the substrate in the logic device region, wherein the first gate structure comprises a single-layer polysilicon. A second gate structure for a memory cell is disposed over the substrate in the memory cell region. The second gate structure includes a gate insulating layer on the substrate. A floating gate layer is disposed on the gate insulating layer, wherein the floating gate layer comprises a first polysilicon layer and a second polysilicon layer as a stacked structure. A memory dielectric layer is disposed on the floating gate layer. A control gate layer is disposed on the memory dielectric layer, wherein the control gate layer and the single-layer polysilicon are originated from a preliminary polysilicon layer in same.

Abstract: A touch panel includes a cover plate, a first adhesive component, and a second adhesive component. The first adhesive component which is adhered underneath the cover plate, includes a plurality of first pattered sensing lines. The second adhesive component which is adhered underneath the first adhesive component, includes a plurality of second pattered sensing lines. The first pattered sensing lines and second pattered sensing lines are electrically insulated from each other.

Abstract: A structure of memory device includes trench isolation lines in a substrate, extending along a first direction. An active region in the substrate is between adjacent two of the trench isolation lines. A dielectric layer is disposed on the active region of the substrate. A floating gate corresponding to a memory cell is disposed on the dielectric layer between adjacent two of the trench isolation lines. The floating gate has a first protruding structure at a sidewall extending along the first direction. A first insulating layer crosses over the floating gate and the trench isolation lines. A control gate line is disposed on the first insulating layer over the floating gate, extending along a second direction intersecting with the first direction. The control gate line has a second protruding structure correspondingly stacked over the first protruding structure of the floating gate.

Abstract: A structure of a memory device and a fabrication method thereof are provided. The structure of the memory device includes a tunneling layer disposed on a substrate. A first oxide/nitride/oxide (ONO) layer is disposed on the substrate abutting to the tunneling layer. A floating gate is disposed on the tunneling layer, wherein a side portion of the floating gate is also disposed on the first ONO layer. A second ONO layer is disposed on the floating gate. A control gate is disposed on the second ONO layer. An isolation layer is disposed on first sidewalls of the floating gate and sidewalls of the control gate. An erase gate is disposed on the first ONO layer, wherein the erase gate is isolated from the floating gate and the control gate by the isolation layer.

Abstract: A structure of a memory device and a fabrication method thereof are provided. The structure of the memory device includes a tunneling layer disposed on a substrate. A first oxide/nitride/oxide (ONO) layer is disposed on the substrate abutting to the tunneling layer. A floating gate is disposed on the tunneling layer, wherein a side portion of the floating gate is also disposed on the first ONO layer. A second ONO layer is disposed on the floating gate. A control gate is disposed on the second ONO layer. An isolation layer is disposed on first sidewalls of the floating gate and sidewalls of the control gate. An erase gate is disposed on the first ONO layer, wherein the erase gate is isolated from the floating gate and the control gate by the isolation layer.