Abstract: A method of generating a netlist of an IC device includes extracting dimensions of a gate region of the IC device, the dimensions including a width of the gate region, the width extending at least from a first edge of an active region to a second edge of the active region, and a distance from a first end of the width to a gate via positioned along the width. A first gate resistance value corresponding to the gate region is received, a second gate resistance value is determined based on the distance and the width, and the netlist is updated based on the first and second gate resistance values.

Abstract: A structure of nonvolatile memory device includes a substrate, having a logic device region and a memory cell region. A first gate structure for a low-voltage transistor is disposed over the substrate in the logic device region, wherein the first gate structure comprises a single-layer polysilicon. A second gate structure for a memory cell is disposed over the substrate in the memory cell region. The second gate structure includes a gate insulating layer on the substrate. A floating gate layer is disposed on the gate insulating layer, wherein the floating gate layer comprises a first polysilicon layer and a second polysilicon layer as a stacked structure. A memory dielectric layer is disposed on the floating gate layer. A control gate layer is disposed on the memory dielectric layer, wherein the control gate layer and the single-layer polysilicon are originated from a preliminary polysilicon layer in same.

Abstract: A touch panel includes a cover plate, a first adhesive component and a second adhesive component. The first adhesive component which is adhered underneath the cover plate, includes a plurality of first pattered sensing lines. The second adhesive component which is adhered underneath the first adhesive component, includes a plurality of second pattered sensing lines. The first pattered sensing lines and second pattered sensing lines are electrically insulated from each other.

Abstract: A wireless charging device of game machines, which comprises a game machine, provided with at least a table top, and the table top is provided with at least a concave tray; at least a wireless charging device, located in the concave tray of the table top; there is a panel at the top of the table top of the game machine, and the panel covers the wireless charging device in the tray; the wireless charging device comprises a wireless charging part and a charging support connected to each other. Thereby, the 3C product can be charged without a USB cable, it can be directly placed on the table top with a wireless charging device of game machine for wireless charging.

Abstract: An endoscope device and a cable assembly thereof are provided. The cable assembly includes a first substrate, a second substrate, and a wire. The first substrate includes a first body and a first solder pad disposed on the first body. The second substrate is correspondingly disposed on the first substrate and includes a second body, a second solder pad disposed on the second body and corresponding to the first solder pad, and an accommodating portion corresponding to the second solder pad. The wire includes a soldering portion disposed in the accommodating portion. The first solder pad and the second solder pad are coupled to each other by at least one of a first solder and a second solder, and the soldering portion and the second solder pad are coupled to each other by the first solder.

Abstract: A structure of nonvolatile memory device includes a substrate, having a logic device region and a memory cell region. A first gate structure for a low-voltage transistor is disposed over the substrate in the logic device region, wherein the first gate structure comprises a single-layer polysilicon. A second gate structure for a memory cell is disposed over the substrate in the memory cell region. The second gate structure includes a gate insulating layer on the substrate. A floating gate layer is disposed on the gate insulating layer, wherein the floating gate layer comprises a first polysilicon layer and a second polysilicon layer as a stacked structure. A memory dielectric layer is disposed on the floating gate layer. A control gate layer is disposed on the memory dielectric layer, wherein the control gate layer and the single-layer polysilicon are originated from a preliminary polysilicon layer in same.

Abstract: An article for mounting to a vertical surface comprising a substrate having a first layer formed from a flexible film or sheet and a second layer formed with a conventional low-tack non-reactive reusable adhesive effective for attaching the substrate to drywall or plaster or wood surfaces. At least one rigid component is attached to the substrate. The second layer covers at least a portion of the first layer for attaching to a vertical surface and includes a release area, wherein the release area is positioned such that it is vertically above the at least one rigid component. The rigid component operates to produce a cantilever moment and wherein the release area operates to counteract the cantilever moment.

Abstract: A method of generating a netlist of an IC device includes extracting dimensions of a gate region of the IC device, the dimensions including a width of the gate region, the width extending at least from a first edge of an active region to a second edge of the active region, and a distance from a first end of the width to a gate via positioned along the width. A first gate resistance value corresponding to the gate region is received, a second gate resistance value is determined based on the distance and the width, and the netlist is updated based on the first and second gate resistance values.

Abstract: The present disclosure relates to a hub apparatus and associated charging systems. In some embodiments, the hub apparatus includes (1) a housing assembly defining an internal space; (2) a shaft positioned to extend through the housing assembly; (3) a stator assembly fixedly coupled to the shaft; (4) a side cover fixedly coupled to the shaft and rotatably coupled to the housing assembly, the side cover having a base portion and a mating portion extending from the base portion; and (5) a pair of first connectors positioned through the mating portion. Each of the first connectors comprising a terminal end and a contact portion. The terminal end is electrically coupled to a battery assembly via a wire bundle fixedly coupled to the side cover. The contact portion is configured to electrically couple to an external power source so as to charge the battery assembly through a wired connection.

Abstract: A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer.

Abstract: A stator includes a stator core including stator poles and a yoke connecting the stator poles, at least one winding wound around the stator core and connecting terminals configured to connect with an external power source to supply power to the winding and located at one end of the yoke adjacent the stator poles. A single phase motor and a ventilation fan are also provided.

Abstract: A method of manufacturing FinFET semiconductor devices in memory regions and logic regions includes the steps of forming a first gate material layer on a substrate and fins, patterning the first gate material layer to form a control gate, forming a second gate material layer on the substrate and fins, performing an etch process to the cell region so that the second gate material layer in the cell region is lower than the second gate material layer in the peripheral region, patterning the second gate material layer to form a select gate in the cell region and a dummy gate in the logic region respectively.

Abstract: The present disclosure relates to hub apparatuses and associated systems. An embodiment of the hub apparatus includes a rotor assembly, a shaft, and a stator assembly. The rotor assembly includes first/second housing components and multiple magnets mounted on one or both of the first and second housing components. The stator assembly includes (1) a coil assembly positioned corresponding to the magnets; (2) a main circuit board fixedly coupled to the coil assembly; and (3) a battery assembly positioned inside the coil assembly and carried by the main circuit board.

Abstract: The present disclosure relates to security mechanisms for electric motors and associated systems. For example, the present technology includes a powertrain assembly having (1) a motor having multiple sets of coils; (2) a drive circuitry electrically coupled to the multiple sets of coils; and (3) a security unit electrically coupled to the drive circuitry and the multiple sets of coils. The security unit is configured to short-circuit at least one set of the multiple sets of coils responsive to a signal from a controller. The signal indicates that the motor is, or has been, turned off.

Abstract: A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer.

Abstract: A hybrid vapor phase-solution phase CZT(S,Se) growth technique is provided. In one aspect, a method of forming a kesterite absorber material on a substrate includes the steps of: depositing a layer of a first kesterite material on the substrate using a vapor phase deposition process, wherein the first kesterite material includes Cu, Zn, Sn, and at least one of S and Se; annealing the first kesterite material to crystallize the first kesterite material; and depositing a layer of a second kesterite material on a side of the first kesterite material opposite the substrate using a solution phase deposition process, wherein the second kesterite material includes Cu, Zn, Sn, and at least one of S and Se, wherein the first kesterite material and the second kesterite material form a multi-layer stack of the absorber material on the substrate. A photovoltaic device and method of formation thereof are also provided.

Abstract: A method of manufacturing FinFET semiconductor devices in memory regions and logic regions includes the steps of forming a first gate material layer on a substrate and fins, patterning the first gate material layer to form a control gate, forming a second gate material layer on the substrate and fins, performing an etch process to the cell region so that the second gate material layer in the cell region is lower than the second gate material layer in the peripheral region, patterning the second gate material layer to form a select gate in the cell region and a dummy gate in the logic region respectively.

Abstract: A hybrid vapor phase-solution phase CZT(S,Se) growth technique is provided. In one aspect, a method of forming a kesterite absorber material on a substrate includes the steps of: depositing a layer of a first kesterite material on the substrate using a vapor phase deposition process, wherein the first kesterite material includes Cu, Zn, Sn, and at least one of S and Se; annealing the first kesterite material to crystallize the first kesterite material; and depositing a layer of a second kesterite material on a side of the first kesterite material opposite the substrate using a solution phase deposition process, wherein the second kesterite material includes Cu, Zn, Sn, and at least one of S and Se, wherein the first kesterite material and the second kesterite material form a multi-layer stack of the absorber material on the substrate. A photovoltaic device and method of formation thereof are also provided.

Abstract: A nonvolatile memory cell includes a substrate having a drain region, a source region, and a channel region between the drain region and the source region. A floating gate and a select gate are disposed on the channel region. A control gate is disposed on the floating gate. An erase gate is disposed on the source region. The erase gate includes a lower end portion that extends into a major surface of the substrate.

Abstract: A multi-phase power controller coupled to resonant power converting circuits providing an output voltage is disclosed. The multi-phase power controller includes a current sensing unit, a frequency adjusting circuit and a duty cycle adjusting circuit. The current sensing unit, coupled to a first resonant power converting circuit, provides a first sensing current. The frequency adjusting circuit includes an error amplifier and a first ramp signal generation circuit. The error amplifier provides an error signal according to the output voltage and a reference voltage. The first ramp signal generation circuit provides a first ramp signal according to the error signal. The duty cycle adjusting circuit provides a first PWM signal to the first resonant power converting circuit according to a default voltage and the first ramp signal. The change of the duty cycle of the first PWM signal is related to the first sensing current, the default voltage and the first ramp signal.