Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary manufacturing method includes providing a workpiece that includes a substrate, first channel members and second channel members over the substrate, a first gate structure engaging the first channel members, a second gate structure engaging the second channel members, a dielectric fin disposed between the first and second gate structures, an isolation feature disposed under the dielectric fin. The method also includes forming a metal cap layer at the frontside of the workpiece and depositing a dielectric feature on the dielectric fin. The dielectric feature dividing the metal cap layer into a first segment and a second segment. The method also includes etching the isolation feature to form a trench at the backside of the substrate, depositing a spacer on sidewalls of the trench, etching the dielectric fin from the trench, and depositing a seal layer in the trench.

Abstract: A circuit board comprises a substrate with opposite first and second sides. A pair of plated through holes (PTHs) extends along z-axis. A pair of signal traces are made on the first side of the substrate and electrically coupled to the pair of the PTHs respectively to form a differential pair. A ground metal is made on the second side of the substrate, the ground metal has a clearance made therein. The ground metal extends fully overlapping with the full signal traces to eliminate reflection noise caused by a boundary between the clearance and the metal ground.

Abstract: In some embodiments, a keyboard key structure includes: a substrate; a key switch, which includes a top housing, a bottom housing. and a key stem. The top housing covers the key stem and is coupled to the bottom housing to form a cavity. The bottom housing is coupled to the substrate. The keyboard key structure further include a keycap including a light transmissive region, the keycap being configured to be coupled to the top housing of the key switch; and a light guide coupled to one side of the cavity of the key switch, the light guide comprising: a flat bottom surface; and a flat top surface wider than and parallel to the bottom surface. The top surface includes uncontinuous, trapezoidal-shaped Fresnel structures at end portions at both ends thereof. A light emitting element is coupled to the substrate and disposed under the bottom surface.

Abstract: A trajectory predicting method and a computing system for trajectory prediction are provided. In the method, feature extraction is respectively performed on past trajectories of multiple target objects through an encoder to generate first trajectory information of the target objects. A pooling process is performed on the first trajectory information of the target objects to generate second trajectory information of the target objects. The second trajectory information of each target object includes location relationships relative to other target objects. Third trajectory information is obtained from the past trajectories of the target objects. The third trajectory information includes a moving direction, scene information, and/or a moving mode. The predicted trajectories of the target objects are generated according to the second trajectory information and the third trajectory information through a decoder. Accordingly, the accuracy of prediction can be improved.

Abstract: A hybrid printed circuit board (PCB) topology is provided. A non-volatile storage system may include a PCB, a first non-volatile storage device attached to a first side of the PCB, a second non-volatile storage device attached to a second side of the PCB, and a storage controller coupled to the first and second non-volatile storage devices by a shared channel. The two devices may be placed in a clamshell configuration but have different capacities. The shared channel may have a first signal route to a first pin of the first non-volatile storage device and a second signal route to a second pin of the second non-volatile storage device. The first pin may have a pin capacitance that is smaller than that of the second pin. The first signal route has an extra resistor in series compared to the second signal route.

Abstract: The invention pertains to the technical field of semiconductor devices, and specifically relates to a three-dimensional capacitor-inductor based on a high-functional-density through silicon via structure and a manufacturing method, The three-dimensional capacitor-inductor of the present invention includes: a substrate formed with a through silicon via; a three-dimensional capacitor, formed on a sidewall of the through silicon via, and sequentially including a first metal layer, a second insulating layer; and a second metal layer; and a three-dimensional inductor, composed of center-filled metal of the through silicon via and planar thick metal rewiring, wherein a first insulating layer is provided between the sidewall of the through silicon via and the three-dimensional capacitor, and a third insulating layer is provided between the three-dimensional capacitor and the three-dimensional inductor, The invention can effectively increase the values of capacitance and inductance in an integrated system, and at the

Abstract: In a mask review method, a vacuum is drawn in a vacuum chamber that contains an extreme ultraviolet (EUV) actinic mask review system including an EUV illuminator, a mask stage, a projection optics box, and an EUV imaging sensor. With the vacuum drawn, a position is adjusted of at least one component of the EUV actinic mask review system. After the adjusting and with the vacuum drawn, an actinic image is acquired of an EUV mask mounted on the mask stage using the EUV imaging sensor. The acquiring includes transmitting EUV light from the EUV illuminator onto the EUV mask and projecting at least a portion of the EUV light reflected by the EUV mask onto the EUV imaging sensor using the projection optics box.

Abstract: Systems, apparatus and methods are provided for low temperature management of a storage system. An apparatus may include a temperature sensor to generate a temperature reading, a timer configured with a time interval, a backup battery, one or more non-volatile memory (NVM) devices and a storage controller. The storage controller may be configured to: maintain a standby mode for low temperature management until a host electronic system has been turned off, start the timer and check the temperature reading when the host electronic system is turned off, determine that the temperature reading is below a temperature threshold, set the time interval based on the temperature reading, receive an interrupt from the timer when the timer counts to the time Interval, and perform low-temperature management operations for data stored in the one or more NVM devices using power supplied by the backup battery.

Abstract: A semiconductor device includes a substrate, a channel member above the substrate, a gate structure engaging the channel member, an epitaxial feature in physical contact with the channel member, and a dielectric layer interposing the gate structure and the epitaxial feature. A sidewall surface of the dielectric layer facing the gate structure has a convex shape in a top view, and the convex shape has a center portion extending towards the gate structure.

Abstract: A system and method for improving the ability of a camera to detect objects or events occurring within its field of view and to accurately categorize them using Artificial Intelligence (AI) aided by input from users. The camera may include rules for determining when an object has entered its field of view, and for determining what category of object it is. When a new object is detected, an alert may be sent to a user and optionally to an analytics service as well. The user may provide input confirming whether the category of the event was correctly determined, and the analytics service may apply an AI algorithm to determine what, if any, changes should be made to the rule criteria in the camera. Updated rule criteria may be sent back to the camera thus improving its ability to detect objects in the future.

Abstract: The present disclosure relates to a method for predicting an amount of water-sealed gas in a high-sulfur water-bearing gas reservoir. The method solves the problem that no method has yet been proposed for predicting the amount of water-sealed gas in a high-sulfur water-bearing gas reservoir. According to the technical solution, the method includes: considering that the volume of the gas reservoir does not change during the production of the constant-volume gas reservoir, deriving, based on a material balance method, a material balance equation of the high-sulfur water-bearing gas reservoir in consideration of water-sealed gas and water-soluble gas, solving and drawing a chart of water-sealed gas in the high-sulfur water-bearing gas reservoir by an iterative algorithm, obtaining a recovery factor of the high-sulfur water-bearing gas reservoir in consideration of water-sealed gas and water-soluble gas, and further obtaining the amount of water-seal gas in the high-sulfur water-bearing gas reservoir.

Abstract: Provided herein are non-invasive and non-destructive methods for classifying the type of external corrosion defect and the severity thereof in the cathodic protection system on a buried pipeline. Mathematical tools and algorithms are utilized to classify the type and the severity of the corrosion defect.

Abstract: A method and apparatus for carrier aggregation is disclosed. In one embodiment, a method performed by a first wireless communication node, comprising: receiving a downlink signal containing first information from a second wireless communication node, and based on at least a portion of the first information, determining first resource information to perform sidelink communication between the first wireless communication node and at least one third wireless communication node.

Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a substrate having a p-type well or an n-type well, a first base portion over the p-type well, a second base portion over the n-type well, a first plurality of channel members over the first base portion, a second plurality of channel members over the second base portion, an isolation feature disposed between the first base portion and the second base portion, and a deep isolation structure in the substrate disposed below the isolation feature.

Abstract: This disclosure provides for robust isolation across the SOI structure. In contrast to forming a charge trap layer in specific areas on the structure, a charge trap layer may be built across the insulating/substrate interface. The charge trap layer may be an implantation layer formed throughout and below the insulation layer. Devices built on this SOI structure have reduced cross-talk between the devices. Due to the uniform structure, isolation is robust across the structure and not confined to certain areas. Additionally, deep trench implantation is not required to form the structure, eliminating cost. The semiconductor-on-insulator substrate may include an active silicon layer over an oxide layer. The oxide layer may be over a charge trap layer. The charge trap layer may be over a silicon substrate.

Abstract: A supporting device is provided and includes: a base; an upright column disposed on the base; a lifting module disposed on the upright column; a constant force arm unit including: a first rotating member rotatably disposed on the upright column and defining a constant first effective force arm; and a first wire wound on the first rotating member; a variable force arm unit including: a second rotating member linked with the first rotating member and defining a variable second effective force arm; and a second wire wound on the second rotating member; and an elastic force module connected to the first wire; where the torques respectively generated in the first wire and the second wire are balanced with each other.

Abstract: Disclosed is a three-dimensional integrated system for DRAM chips and a fabrication method thereof. A plurality of trench structures are etched on the front and back of a silicon wafer; then, a TSV structure is etched between the two upper and lower trenches opposite to each other for electrical connection; then, DRAM chips are placed in the trenches, and copper-copper bonding is used to make the chips electrically connected to the TSV structure in a vertical direction; finally, redistribution is done to make the chips in a horizontal direction electrically connected. The invention can make full use of silicon materials, and can avoid problems such as warpage and deformation of an interposer. In addition, placing the chips in the trenches will not increase the overall package thickness, while protecting the chips from external impact.

Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a dielectric feature comprising a first dielectric layer and a second dielectric layer, the first dielectric layer has a first sidewall and a second sidewall opposing the first sidewall, and the second dielectric layer is in contact with at least a portion of the first sidewall and at least a portion of the second sidewall. The structure also includes a first semiconductor layer adjacent the first sidewall, wherein the first semiconductor layer is in contact with the second dielectric layer. The structure further includes a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, wherein the first gate electrode layer has a surface facing the second dielectric layer, and the surface extends over a plane defined by an interface between the second dielectric layer and the first semiconductor layer.

Abstract: An information processing method, an interconnection device, and a computer-readable storage medium are provided. The interconnection device includes a request processing module configured for: receiving a data access request from at least one processor, wherein the data access request comprises a merge bit, a multicast group identifier (MGID), and a multicast transaction identifier (MTID); determining whether the data access request is a multicast request; determining whether the interconnection device receives other multicast requests if it is determined that the data access request is a multicast request based on the MGID, the MTID, and a static routing policy of a multicast group; and obtaining the other multicast requests if it is determined that the interconnection device receives the other multicast requests, merging the multicast request with the other multicast requests into a merged request, and forwarding the merged request to a next-hop device of the interconnection device.