Abstract: A hinge assembly for an electronic device includes a joint assembly including joint components hinged one by one. Each joint component includes a first plate, a second plate, and a link component disposed between the first and second plates. Each of the first and second plates has two first slots diametrically extending in a first direction. The first plate has a second slot disposed between the two first slots and diametrically extending in a second direction different from the first direction. The second plate has a third slot disposed between the two first slots and diametrically extending in a third direction mirror-symmetrical to the second direction with respect to the first direction. The link component has an engaging hole and a guide portion. The engaging hole is corresponding to one of the first slots of each of the first and second plates, and the guide portion is formed on a surface of the link component and movable within the second or third slot.

Abstract: A foldable display device includes a first plate member, a second plate member, a hinge assembly, and a flexible display member. The first plate member includes a first display surface and a first side. The second plate member includes a second display surface and a second side. The first side and the second side are close to each other. A first hinge member and a second hinge member of the hinge assembly are respectively connected to the first plate member and the second plate member. The flexible display member includes a first portion, a second portion, and a middle portion. The first portion contacts the first display surface. The second portion contacts the second display surface. The middle portion is between the first side and the second side. The first and second hinge members rotate relatively to have the flexible display member spread to be flat.

Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

Abstract: A tunable matching circuit for use with ultra-low power RF receivers is described to support a variety of RF communication bands. A switched-capacitor array and a switched-resistor array are used to adjust the input impedance presented by the operating characteristics of transistors in an ultra-low-power mode. An RF sensor may be used to monitor performance of the tunable matching circuit and thereby determine optimal setting of the digital control word that drives the switched-capacitor array and switched-resistor array. An effective match over a significant bandwidth is achievable. The optimal matching configuration may be updated at any time to adjust to changing operating conditions. Memory may be used to store the optimal matching configurations of the switched capacitor array and switched resistor array.

Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

Abstract: An integrated circuit (IC) structure is provided. The IC structure comprises a deep n-well (DWN), a first circuit, a second circuit, a first power line and a second power line. The first circuit is in the DWN. The second circuit is outside the DWN and electrically connected with the first circuit. The first power line is configured to provide the first circuit with power. The second power line is configured to provide the second circuit with power. The second power line is electrically connected with the first power line. The first power line and the second power line are in different conductive layers.

Abstract: A method for controlling flash includes obtaining a color temperature of a current environment from a sensor of an electronic device. Once a first flash of a flash is turned on, a color temperature of the first flash is controlled to be equal to the color temperature of the current environment by adjusting a ratio between current of a high color temperature light-emitting diode (LED) of the electronic device and current of a low color temperature LED of the electronic device.

Abstract: A heat dissipation device includes a mounting bracket and a thermal module. The mounting bracket has at least one retaining hole and a mounting section, and the thermal module includes a plurality of radiating fins, to which the mounting bracket is connected. On the radiating fins, at least one engaging zone is provided for correspondingly engaging with the mounting bracket, and at least one locking portion is formed for correspondingly engaging with the retaining hole. With the above structural design, the mounting bracket can be more firmly and stably connected to the thermal module and be more accurately located on the radiating fins without the need of welding, so that the manufacturing cost for welding is saved. A method of manufacturing the heat dissipation device is also disclosed.

Abstract: A thermal module assembling structure includes a heat sink, at least one leaf spring, at least one holding member and a shaft rod. The heat sink has a base seat and multiple radiating fins disposed on the base seat. At least one perforation is formed on each of two opposite sides of the base seat. The heat sink is correspondingly assembled on the leaf spring. At least one engagement post is disposed on the leaf spring corresponding to the perforation. The holding member is slidably capped on the engagement post and has a first end and a second end. The second end is formed with a socket having an internal receiving space in which a raised section is formed. The engagement post is inlaid in the receiving space. The shaft rod passes through the heat sink. Two ends of the shaft rod are respectively connected with the engagement posts.

Abstract: A method for controlling flash includes obtaining a color temperature of a current environment from a sensor of an electronic device. Once a first flash of a flash is turned on, a color temperature of the first flash is controlled to be equal to the color temperature of the current environment by adjusting a ratio between current of a high color temperature light-emitting diode (LED) of the electronic device and current of a low color temperature LED of the electronic device.

Abstract: A heat dissipation device includes a mounting bracket and a thermal module. The mounting bracket has at least one retaining hole and a mounting section, and the thermal module includes a plurality of radiating fins, to which the mounting bracket is connected. On the radiating fins, at least one engaging zone is provided for correspondingly engaging with the mounting bracket, and at least one locking portion is formed for correspondingly engaging with the retaining hole. With the above structural design, the mounting bracket can be more firmly and stably connected to the thermal module and be more accurately located on the radiating fins without the need of welding, so that the manufacturing cost for welding is saved. A method of manufacturing the heat dissipation device is also disclosed.

Abstract: An electronic device is disclosed that includes an output device and a detection circuit. The output device is coupled to an output pad, and is turned on according to a protection signal. The detection circuit is configured to detect a voltage level of a control node, to generate the protection signal based on the detected voltage level, and to switch the voltage level to a predetermined voltage level according to the detected voltage level.

Abstract: A circuit that includes a first diode-connected dummy device, a second diode-connected dummy device, a third diode-connected dummy device, a fourth diode-connected dummy device, and a first discharge path. The second diode-connected dummy device connected in cascode with the first diode-connected dummy device. The fourth diode-connected dummy device connected in cascode with the third diode-connected dummy device. The first and the second diode-connected dummy devices are formed in a first region. The third and the fourth diode-connected dummy devices are formed in a second region which is outside the first region. The first discharge path configured to discharge charges from at least one of the first and the second diode-connected dummy devices in the first region to a reference voltage terminal of one of the third and the fourth diode-connected dummy devices in the second region.

Abstract: A method for controlling a flash of an electronic device by detecting an illumination intensity and a color temperature of a current environment from a RGB sensor. When the illumination intensity is lower than a first predetermined value, a pre-flash of the flash is turned on. Control a color temperature of the pre-flash to be equal to the color temperature when the color temperature is lower than a second predetermined value. A distance between a target object and the camera is obtained, adjusting the current of the high color temperature LED and the current of the low color temperature LED simultaneously according to the obtained distance after turning on a main-flash of the flash to capture an image of the target object.

Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.

Abstract: A communication device integrally formed with antenna and mask is provided. The communication device comprises a circuit board, a frame, a communication chip and a mask. The frame is disposed on an upper surface of the circuit board. The frame has multiple sidewalls perpendicular to the upper surface and surrounding an opening. The communication chip is disposed on the upper surface and located in the opening. The mask is disposed on the circuit board, comprises a cover, multiple plates and an antenna module. The cover covers the communication chip. The plate is projected from a lower edge of the cover and parallel to the sidewalls, and has a hollowed area. The antenna module is connected to the hollowed area and integrally formed with the plate in one piece.

Abstract: Pharmaceutical preparations containing polypeptides having particular sialylation patterns, and methods for the treatment of immune-related thrombocytopenia with such preparations, are described.

Abstract: A compound, and a polymer prepared therefrom, are provided. The compound has a structure represented by Formula (I) or Formula (II): wherein A is R1 is C1-10 alkyl, C5-12 cycloalkyl, C6-14 aryl, C3-12 heteroaryl, C1-10 alkoxy, C6-12 aryloxy, C1-10 silyl, amino, thiol, or phosphonate group; R2 is H, or C1-10 alkyl; and, R3 is C1-10 alkoxy, C1-10 alkanol, amine, or hydroxy.

Abstract: Compounds having the structure of Formula I, including pharmaceutically acceptable salts of the compounds, are CETP inhibitors and may be useful for raising HDL-cholesterol and reducing LDL-cholesterol in human patients and for treating or preventing atherosclerosis.